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bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)

This commit is contained in:
Florent Kermarrec 2015-06-19 08:37:16 +02:00
parent 7d8f4d1009
commit 71627cf9f0
1 changed files with 1 additions and 3 deletions
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4
migen/bus/wishbone.py
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@ -4,7 +4,6 @@ from migen.genlib.record import *
from migen.genlib.misc import split, displacer, optree, chooser from migen.genlib.misc import split, displacer, optree, chooser
from migen.genlib.misc import FlipFlop, Counter from migen.genlib.misc import FlipFlop, Counter
from migen.genlib.fsm import FSM, NextState from migen.genlib.fsm import FSM, NextState
from migen.bank.description import *
from migen.bus.transactions import * from migen.bus.transactions import *
_layout = [ _layout = [
@ -409,14 +408,13 @@ class Converter(Module):
Record.connect(master, slave) Record.connect(master, slave)
class Cache(Module, AutoCSR): class Cache(Module):
"""Cache """Cache
This module is a write-back wishbone cache that can be used as a L2 cache. This module is a write-back wishbone cache that can be used as a L2 cache.
Cachesize (in 32-bit words) is the size of the data store and must be a power of 2 Cachesize (in 32-bit words) is the size of the data store and must be a power of 2
""" """
def __init__(self, cachesize, master, slave): def __init__(self, cachesize, master, slave):
self._size = CSRStatus(8, reset=log2_int(cachesize))
self.master = master self.master = master
self.slave = slave self.slave = slave