cpu/gowin_emcu: Add interfaces directly to instances and simplify/cleanup to remove some warnings.
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@ -13,7 +13,7 @@ from litex.soc.cores.cpu import CPU
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import ahb
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from litex.soc.interconnect import ahb
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# Gowin EMCU ---------------------------------------------------------------------------------------
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# Gowin EMCU (Enhanced MCU / Cortex M3) ------------------------------------------------------------
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class GowinEMCU(CPU):
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class GowinEMCU(CPU):
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variants = ["standard"]
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variants = ["standard"]
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@ -62,6 +62,9 @@ class GowinEMCU(CPU):
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# -------------
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# -------------
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bus_reset_n = Signal()
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bus_reset_n = Signal()
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ahb_flash = ahb.AHBInterface(data_width=32, address_width=32)
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ahb_targexp0 = ahb.AHBInterface(data_width=32, address_width=32)
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self.cpu_params = dict(
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self.cpu_params = dict(
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# Clk/Rst.
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# Clk/Rst.
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i_FCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys"),
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@ -71,20 +74,95 @@ class GowinEMCU(CPU):
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o_MTXHRESETN = bus_reset_n,
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o_MTXHRESETN = bus_reset_n,
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# RTC.
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# RTC.
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i_RTCSRCCLK = Signal(), # TODO: RTC Clk In.
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i_RTCSRCCLK = 0b0, # RTC Clk In.
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# GPIOs.
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# GPIOs.
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i_IOEXPINPUTI = Signal(), # TODO: GPIO Input (16-bit).
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i_IOEXPINPUTI = 0x0000, # GPIO Input (16-bit).
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o_IOEXPOUTPUTO = Signal(), # TODO: GPIO Output (16-bit).
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o_IOEXPOUTPUTO = Open(16), # GPIO Output (16-bit).
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o_IOEXPOUTPUTENO = Signal(), # TODO: GPIO Output Enable (16-bit).
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o_IOEXPOUTPUTENO = Open(16), # GPIO Output Enable (16-bit).
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# UART0.
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i_UART0RXDI = 0b0,
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o_UART0TXDO = Open(),
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o_UART0BAUDTICK = Open(),
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# UART1.
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i_UART1RXDI = 0b0,
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o_UART1TXDO = Open(),
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o_UART1BAUDTICK = Open(),
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# Interrupts.
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# Interrupts.
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i_GPINT = Open(),
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i_GPINT = 0,
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o_INTMONITOR = Signal(),
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o_INTMONITOR = Open(),
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# Flash.
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# Flash.
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i_FLASHERR = Signal(),
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i_FLASHERR = Signal(),
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i_FLASHINT = Signal(),
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i_FLASHINT = Signal(),
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# Debug/JTAG.
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o_DAPTDO = Open(),
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o_DAPJTAGNSW = Open(),
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o_DAPNTDOEN = Open(),
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i_DAPSWDITMS = 0,
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i_DAPTDI = 0,
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i_DAPNTRST = 0,
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i_DAPSWCLKTCK = 0,
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# TARGFLASH0 / AHBLite Master.
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o_TARGFLASH0HSEL = ahb_flash.sel,
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o_TARGFLASH0HADDR = ahb_flash.addr,
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o_TARGFLASH0HTRANS = ahb_flash.trans,
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o_TARGFLASH0HSIZE = ahb_flash.size,
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o_TARGFLASH0HBURST = ahb_flash.burst,
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o_TARGFLASH0HREADYMUX = Open(),
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i_TARGFLASH0HRDATA = ahb_flash.rdata,
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i_TARGFLASH0HRUSER = 0b000,
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i_TARGFLASH0HRESP = ahb_flash.resp,
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i_TARGFLASH0EXRESP = 0b0,
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i_TARGFLASH0HREADYOUT = ahb_flash.readyout,
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# TARGEXP0 / AHBLite Master.
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o_TARGEXP0HSEL = ahb_targexp0.sel,
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o_TARGEXP0HADDR = ahb_targexp0.addr,
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o_TARGEXP0HTRANS = ahb_targexp0.trans,
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o_TARGEXP0HWRITE = ahb_targexp0.write,
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o_TARGEXP0HSIZE = ahb_targexp0.size,
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o_TARGEXP0HBURST = ahb_targexp0.burst,
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o_TARGEXP0HPROT = ahb_targexp0.prot,
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o_TARGEXP0MEMATTR = Open(2),
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o_TARGEXP0EXREQ = Open(),
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o_TARGEXP0HMASTER = Open(4),
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o_TARGEXP0HWDATA = ahb_targexp0.wdata,
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o_TARGEXP0HMASTLOCK = ahb_targexp0.mastlock,
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o_TARGEXP0HREADYMUX = Open(),
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o_TARGEXP0HAUSER = Open(),
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o_TARGEXP0HWUSER = Open(4),
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i_TARGEXP0HRDATA = ahb_targexp0.rdata,
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i_TARGEXP0HREADYOUT = ahb_targexp0.readyout,
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i_TARGEXP0HRESP = ahb_targexp0.resp,
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i_TARGEXP0EXRESP = 0b0,
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i_TARGEXP0HRUSER = 0b000,
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# INITEXP0 / AHBLite Slave.
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o_INITEXP0HRDATA = Open(32),
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o_INITEXP0HREADY = Open(),
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o_INITEXP0HRESP = Open(),
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o_INITEXP0EXRESP = Open(),
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o_INITEXP0HRUSER = Open(3),
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i_INITEXP0HSEL = 0b0,
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i_INITEXP0HADDR = 0x00000000,
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i_INITEXP0HTRANS = 0b00,
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i_INITEXP0HWRITE = 0b0,
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i_INITEXP0HSIZE = 0b000,
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i_INITEXP0HBURST = 0b000,
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i_INITEXP0HPROT = 0b0000,
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i_INITEXP0MEMATTR = 0b00,
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i_INITEXP0EXREQ = 0b0,
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i_INITEXP0HMASTER = 0b0000,
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i_INITEXP0HWDATA = 0x00000000,
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i_INITEXP0HMASTLOCK = 0b0,
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i_INITEXP0HAUSER = 0b0,
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i_INITEXP0HWUSER = 0b0000,
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)
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)
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# SRAM (32-bit RAM split between 4 SRAMs x 8-bit each).
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# SRAM (32-bit RAM split between 4 SRAMs x 8-bit each).
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@ -111,6 +189,10 @@ class GowinEMCU(CPU):
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p_BIT_WIDTH_0 = 8,
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p_BIT_WIDTH_0 = 8,
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p_BIT_WIDTH_1 = 8,
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p_BIT_WIDTH_1 = 8,
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p_RESET_MODE = "SYNC",
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p_RESET_MODE = "SYNC",
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p_BLK_SEL_0 = Constant(0, 3),
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p_BLK_SEL_1 = Constant(0, 3),
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i_BLKSELA = 0b000,
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i_BLKSELB = 0b000,
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o_DO = sram0_rdata[8*i:8*(i + 1)],
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o_DO = sram0_rdata[8*i:8*(i + 1)],
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i_DI = sram0_wdata[8*i:8*(i + 1)],
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i_DI = sram0_wdata[8*i:8*(i + 1)],
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i_ADA = Cat(Signal(3), sram0_addr),
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i_ADA = Cat(Signal(3), sram0_addr),
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@ -161,39 +243,12 @@ class GowinEMCU(CPU):
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i_NVSTR = 0
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i_NVSTR = 0
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)
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)
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ahb_flash = ahb.AHBInterface(data_width=32, address_width=32)
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self.cpu_params.update(
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o_TARGFLASH0HADDR = ahb_flash.addr,
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o_TARGFLASH0HBURST = ahb_flash.burst,
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o_TARGFLASH0HSIZE = ahb_flash.size,
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o_TARGFLASH0HTRANS = ahb_flash.trans,
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o_TARGFLASH0HSEL = ahb_flash.sel,
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i_TARGFLASH0HRDATA = ahb_flash.rdata,
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i_TARGFLASH0HREADYOUT = ahb_flash.readyout,
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i_TARGFLASH0HRESP = ahb_flash.resp,
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)
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flash = ResetInserter()(AHBFlash(ahb_flash))
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flash = ResetInserter()(AHBFlash(ahb_flash))
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self.comb += flash.reset.eq(~bus_reset_n)
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self.comb += flash.reset.eq(~bus_reset_n)
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self.submodules += flash
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self.submodules += flash
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# Peripheral Bus (AHB -> Wishbone).
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# Peripheral Bus (AHB -> Wishbone).
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# ---------------------------------
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# ---------------------------------
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ahb_targexp0 = ahb.AHBInterface(data_width=32, address_width=32)
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self.cpu_params.update(
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o_TARGEXP0HADDR = ahb_targexp0.addr,
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o_TARGEXP0HBURST = ahb_targexp0.burst,
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o_TARGEXP0HMASTLOCK = ahb_targexp0.mastlock,
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o_TARGEXP0HPROT = ahb_targexp0.prot,
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o_TARGEXP0HSIZE = ahb_targexp0.size,
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o_TARGEXP0HTRANS = ahb_targexp0.trans,
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o_TARGEXP0HWDATA = ahb_targexp0.wdata,
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o_TARGEXP0HWRITE = ahb_targexp0.write,
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o_TARGEXP0HSEL = ahb_targexp0.sel,
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i_TARGEXP0HRDATA = ahb_targexp0.rdata,
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i_TARGEXP0HREADYOUT = ahb_targexp0.readyout,
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i_TARGEXP0HRESP = ahb_targexp0.resp,
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)
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self.submodules += ahb.AHB2Wishbone(ahb_targexp0, self.pbus)
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self.submodules += ahb.AHB2Wishbone(ahb_targexp0, self.pbus)
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def connect_uart(self, pads, n=0):
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def connect_uart(self, pads, n=0):
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