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Merge pull request #1824 from trabucayre/add_64_bus_support_v2 

soc/interconnect/wishbone: InterconnectShared,Crossbar: using master adr_width for Interface constructor
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enjoy-digital 2023-10-31 21:17:31 +01:00 committed by GitHub
parent 9b8a5b6385 755808e287
commit 71ae8fe828
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1 changed files with 4 additions and 2 deletions
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litex/soc/interconnect/wishbone.py
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@ -238,7 +238,8 @@ class Decoder(LiteXModule):
class InterconnectShared(LiteXModule): class InterconnectShared(LiteXModule):
def __init__(self, masters, slaves, register=False, timeout_cycles=1e6): def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
data_width = get_check_parameters(ports=masters + [s for _, s in slaves]) data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
shared = Interface(data_width=data_width) adr_width = max([m.adr_width for m in masters])
shared = Interface(data_width=data_width, adr_width=adr_width)
self.arbiter = Arbiter(masters, shared) self.arbiter = Arbiter(masters, shared)
self.decoder = Decoder(shared, slaves, register) self.decoder = Decoder(shared, slaves, register)
if timeout_cycles is not None: if timeout_cycles is not None:
@ -249,7 +250,8 @@ class Crossbar(LiteXModule):
def __init__(self, masters, slaves, register=False, timeout_cycles=1e6): def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
data_width = get_check_parameters(ports=masters + [s for _, s in slaves]) data_width = get_check_parameters(ports=masters + [s for _, s in slaves])
matches, busses = zip(*slaves) matches, busses = zip(*slaves)
access = [[Interface(data_width=data_width) for j in slaves] for i in masters] adr_width = max([m.adr_width for m in masters])
access = [[Interface(data_width=data_width, adr_width=adr_width) for j in slaves] for i in masters]
# decode each master into its access row # decode each master into its access row
for row, master in zip(access, masters): for row, master in zip(access, masters):
row = list(zip(matches, row)) row = list(zip(matches, row))