fhdl/verilog: lower complex slices before reset insertion

2013-06-30 14:32:47 +02:00 · 2013-06-30 14:32:47 +02:00 · 71b89e4c46
parent ded5e569eb
commit 71b89e4c46
1 changed files with 1 additions and 0 deletions
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@ -302,6 +302,7 @@ def convert(f, ios=None, name="top",
 			else:
 				raise KeyError("Unresolved clock domain: '"+cd_name+"'")
 	
+	f = lower_complex_slices(f)
 	_insert_resets(f)
 	f = lower_basics(f)
 	fs, lowered_specials = _lower_specials(special_overrides, f.specials)