fhdl/verilog: lower complex slices before reset insertion
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@ -302,6 +302,7 @@ def convert(f, ios=None, name="top",
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else:
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else:
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raise KeyError("Unresolved clock domain: '"+cd_name+"'")
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raise KeyError("Unresolved clock domain: '"+cd_name+"'")
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f = lower_complex_slices(f)
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_insert_resets(f)
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_insert_resets(f)
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f = lower_basics(f)
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f = lower_basics(f)
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fs, lowered_specials = _lower_specials(special_overrides, f.specials)
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fs, lowered_specials = _lower_specials(special_overrides, f.specials)
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