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fhdl/verilog: lower complex slices before reset insertion

This commit is contained in:
Sebastien Bourdeauducq 2013-06-30 14:32:47 +02:00
parent ded5e569eb
commit 71b89e4c46
1 changed files with 1 additions and 0 deletions
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migen/fhdl/verilog.py
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@ -302,6 +302,7 @@ def convert(f, ios=None, name="top",
else: else:
raise KeyError("Unresolved clock domain: '"+cd_name+"'") raise KeyError("Unresolved clock domain: '"+cd_name+"'")
f = lower_complex_slices(f)
_insert_resets(f) _insert_resets(f)
f = lower_basics(f) f = lower_basics(f)
fs, lowered_specials = _lower_specials(special_overrides, f.specials) fs, lowered_specials = _lower_specials(special_overrides, f.specials)