Add GPIO buttons and LEDs

This commit is contained in:
Sebastien Bourdeauducq 2013-05-16 17:43:20 +02:00
parent 581cf5bcb8
commit 71cc2db867
2 changed files with 26 additions and 1 deletions

View File

@ -0,0 +1,20 @@
from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.genlib.cdc import MultiReg
from migen.bank.description import *
class GPIOIn(Module, AutoCSR):
def __init__(self, signal):
self._r_in = CSRStatus(len(signal))
self.specials += MultiReg(signal, self._r_in.status)
class GPIOOut(Module, AutoCSR):
def __init__(self, signal):
self._r_out = CSRStorage(len(signal))
self.comb += signal.eq(self._r_out.storage)
class Blinker(Module):
def __init__(self, signal, divbits=26):
counter = Signal(divbits)
self.comb += signal.eq(counter[divbits-1])
self.sync += counter.eq(counter + 1)

7
top.py
View File

@ -8,7 +8,8 @@ from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
from migen.bank import csrgen
from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler, counteradc
identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler, \
counteradc, gpio
from cif import get_macros
version = get_macros("common/version.h")["VERSION"][1:-1]
@ -78,6 +79,8 @@ class SoC(Module):
"dvisampler1": 10,
"dvisampler1_edid_mem": 11,
"pots": 12,
"buttons": 13,
"leds": 14
}
interrupt_map = {
@ -152,6 +155,8 @@ class SoC(Module):
pots_pads = platform.request("dvi_pots")
self.submodules.pots = counteradc.CounterADC(pots_pads.charge,
[pots_pads.blackout, pots_pads.crossfade])
self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))
self.submodules.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])