Add GPIO buttons and LEDs
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parent
581cf5bcb8
commit
71cc2db867
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@ -0,0 +1,20 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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class GPIOIn(Module, AutoCSR):
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def __init__(self, signal):
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self._r_in = CSRStatus(len(signal))
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self.specials += MultiReg(signal, self._r_in.status)
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class GPIOOut(Module, AutoCSR):
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def __init__(self, signal):
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self._r_out = CSRStorage(len(signal))
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self.comb += signal.eq(self._r_out.storage)
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class Blinker(Module):
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def __init__(self, signal, divbits=26):
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counter = Signal(divbits)
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self.comb += signal.eq(counter[divbits-1])
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self.sync += counter.eq(counter + 1)
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7
top.py
7
top.py
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@ -8,7 +8,8 @@ from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
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from migen.bank import csrgen
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from migen.bank import csrgen
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from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
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from milkymist import m1crg, lm32, norflash, uart, s6ddrphy, dfii, asmicon, \
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identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler, counteradc
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identifier, timer, minimac3, framebuffer, asmiprobe, dvisampler, \
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counteradc, gpio
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from cif import get_macros
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from cif import get_macros
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version = get_macros("common/version.h")["VERSION"][1:-1]
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version = get_macros("common/version.h")["VERSION"][1:-1]
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@ -78,6 +79,8 @@ class SoC(Module):
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"dvisampler1": 10,
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"dvisampler1": 10,
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"dvisampler1_edid_mem": 11,
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"dvisampler1_edid_mem": 11,
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"pots": 12,
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"pots": 12,
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"buttons": 13,
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"leds": 14
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}
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}
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interrupt_map = {
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interrupt_map = {
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@ -152,6 +155,8 @@ class SoC(Module):
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pots_pads = platform.request("dvi_pots")
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pots_pads = platform.request("dvi_pots")
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self.submodules.pots = counteradc.CounterADC(pots_pads.charge,
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self.submodules.pots = counteradc.CounterADC(pots_pads.charge,
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[pots_pads.blackout, pots_pads.crossfade])
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[pots_pads.blackout, pots_pads.crossfade])
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self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
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self.submodules.leds = gpio.GPIOOut(Cat(*[platform.request("user_led", i) for i in range(2)]))
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self.submodules.csrbankarray = csrgen.BankArray(self,
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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