fhdl/memory: First Cleanup/Re-organization pass.
- Reorganize a bit (move Memory initialization to Memory declaration block). - Use f-strings. - Add separators. - Add comments.
This commit is contained in:
Florent Kermarrec
parent
70c5be6fb8
commit
71f8fc7cb5
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@ -1,3 +1,10 @@
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#
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# This file is part of LiteX (Adapted from Migen for LiteX usage).
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#
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# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen.fhdl.structure import *
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from migen.fhdl.module import *
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from migen.fhdl.bitcontainer import bits_for
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@ -6,21 +13,22 @@ from migen.fhdl.verilog import _printexpr as verilog_printexpr
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from migen.fhdl.specials import *
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def memory_emit_verilog(memory, ns, add_data_file):
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r = ""
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# Helpers.
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# --------
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def gn(e):
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if isinstance(e, Memory):
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return ns.get_name(e)
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else:
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return verilog_printexpr(ns, e)[0]
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adrbits = bits_for(memory.depth-1)
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(memory) \
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+ "[0:" + str(memory.depth-1) + "];\n"
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adr_regs = {}
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# Parameters.
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# -----------
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adrbits = bits_for(memory.depth-1)
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adr_regs = {}
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data_regs = {}
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# Ports Transformations.
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# ----------------------
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# https://github.com/enjoy-digital/litex/issues/1003
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# FIXME: Verify behaviour with the different FPGA toolchains.
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clocks = [port.clock for port in memory.ports]
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@ -28,69 +36,99 @@ def memory_emit_verilog(memory, ns, add_data_file):
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for port in memory.ports:
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port.mode = READ_FIRST
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for port in memory.ports:
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if not port.async_read:
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if port.mode == WRITE_FIRST:
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adr_reg = Signal(name_override="memadr")
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r += "reg [" + str(adrbits-1) + ":0] " \
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+ gn(adr_reg) + ";\n"
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adr_regs[id(port)] = adr_reg
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else:
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data_reg = Signal(name_override="memdat")
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r += "reg [" + str(memory.width-1) + ":0] " \
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+ gn(data_reg) + ";\n"
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data_regs[id(port)] = data_reg
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# Memory Declaration/Initialization.
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# ----------------------------------
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r = f"reg [{memory.width-1}:0] {gn(memory)}[0:{memory.depth-1}];\n"
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if memory.init is not None:
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content = ""
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formatter = f"{{:0{int(memory.width/4)}x}}\n"
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for d in memory.init:
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content += formatter.format(d)
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memory_filename = add_data_file(f"{gn(memory)}.init", content)
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r += "initial begin\n"
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r += f"\t$readmemh(\"{memory_filename}\", {gn(memory)});\n"
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r += "end\n\n"
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# Port Intermediate Signals.
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# --------------------------
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for port in memory.ports:
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r += "always @(posedge " + gn(port.clock) + ") begin\n"
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# No Intermediate Signal for Async Read.
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if port.async_read:
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continue
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# Create Address Register in Write-First mode.
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if port.mode in [WRITE_FIRST]:
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adr_reg = Signal(name_override="memadr")
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r += f"reg [{adrbits-1}:0] {gn(adr_reg)};\n"
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adr_regs[id(port)] = adr_reg
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# Create Data Register in Read-First/No Change mode.
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if port.mode in [READ_FIRST, NO_CHANGE]:
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data_reg = Signal(name_override="memdat")
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r += f"reg [{memory.width-1}:0] {gn(data_reg)};\n"
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data_regs[id(port)] = data_reg
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# Ports Write/Read Logic.
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# -----------------------
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for port in memory.ports:
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r += f"always @(posedge {gn(port.clock)}) begin\n"
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# Write Logic.
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if port.we is not None:
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# Split Write Logic when Granularity.
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if port.we_granularity:
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n = memory.width//port.we_granularity
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for i in range(n):
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m = i*port.we_granularity
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M = (i+1)*port.we_granularity-1
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sl = "[" + str(M) + ":" + str(m) + "]"
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r += "\tif (" + gn(port.we) + "[" + str(i) + "])\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "]" + sl + " <= " + gn(port.dat_w) + sl + ";\n"
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sl = f"[{M}:{m}]"
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r += f"\tif ({gn(port.we)}[{i}])\n"
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r += f"\t\t{gn(memory)}[{gn(port.adr)}]{sl} <= {gn(port.dat_w)}{sl};\n"
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# Else use common Write Logic.
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else:
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r += "\tif (" + gn(port.we) + ")\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
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r += f"\tif ({gn(port.we)})\n"
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r += f"\t\t{gn(memory)}[{gn(port.adr)}] <= {gn(port.dat_w)};\n"
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# Read Logic.
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if not port.async_read:
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if port.mode == WRITE_FIRST:
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rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
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else:
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bassign = gn(data_regs[id(port)]) + " <= " + gn(memory) + "[" + gn(port.adr) + "];\n"
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# In Write-First mode, Read from Address Register.
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if port.mode in [WRITE_FIRST]:
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rd = f"\t{gn(adr_regs[id(port)])} <= {gn(port.adr)};\n"
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# In Write-First/No Change mode:
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if port.mode in [READ_FIRST, NO_CHANGE]:
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bassign = f"{gn(data_regs[id(port)])} <= {gn(memory)} [{gn(port.adr)}];\n"
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# Always Read in Read-First mode.
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if port.mode == READ_FIRST:
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rd = "\t" + bassign
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rd = f"\t{bassign}"
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# Only Read in No-Change mode when no Write.
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elif port.mode == NO_CHANGE:
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rd = "\tif (!" + gn(port.we) + ")\n" \
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+ "\t\t" + bassign
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rd = f"\tif (!{gn(port.we)})\n\t\t{bassign}"
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# Add Read-Enable Logic.
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if port.re is None:
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r += rd
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else:
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r += "\tif (" + gn(port.re) + ")\n"
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r += f"\tif ({gn(port.re)})\n"
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r += "\t" + rd.replace("\n\t", "\n\t\t")
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r += "end\n\n"
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# Ports Read Mapping.
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# -------------------
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for port in memory.ports:
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# Direct (Asynchronous) Read on Async-Read mode.
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if port.async_read:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n"
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else:
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if port.mode == WRITE_FIRST:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(adr_regs[id(port)]) + "];\n"
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else:
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r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n"
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r += f"assign {gn(port.dat_r)} = {gn(memory)}[{gn(port.adr)}];\n"
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continue
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# Write-First mode: Do Read through Address Register.
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if port.mode in [WRITE_FIRST]:
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r += f"assign {gn(port.dat_r)} = {gn(memory)}[{gn(adr_regs[id(port)])}];\n"
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# Read-First/No-Change mode: Data already Read on Data Register.
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if port.mode in [READ_FIRST, NO_CHANGE]:
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r += f"assign {gn(port.dat_r)} = {gn(data_regs[id(port)])};\n"
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r += "\n"
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if memory.init is not None:
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content = ""
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formatter = "{:0" + str(int(memory.width / 4)) + "X}\n"
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for d in memory.init:
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content += formatter.format(d)
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memory_filename = add_data_file(gn(memory) + ".init", content)
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r += "initial begin\n"
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r += "\t$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
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r += "end\n\n"
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return r
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