boards/targets/ulx3s: reduce l2_size

2018-10-30 10:14:48 +01:00 · 2018-10-30 10:14:48 +01:00 · 71fc34d7b6
parent 75d073f394
commit 71fc34d7b6
1 changed files with 1 additions and 0 deletions
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@ -52,6 +52,7 @@ class BaseSoC(SoCSDRAM):
        platform = ulx3s.Platform(toolchain="prjtrellis")
        sys_clk_freq = int(25e6)
        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+                          l2_size=32,
                          integrated_rom_size=0x8000,
                          **kwargs)