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test/test_wishbone: Improve origin_region_remap_test to test more complex remapping.

This commit is contained in:
Florent Kermarrec 2024-02-28 19:09:34 +01:00
parent 3d9db91387
commit 722b6da9fb
1 changed files with 15 additions and 8 deletions
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23
test/test_wishbone.py
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@ -274,16 +274,19 @@ class TestWishbone(unittest.TestCase):
"word": 4, "word": 4,
}[addressing] }[addressing]
def generator(dut): def generator(dut):
yield from dut.master.write(0x0000_0000//adr_div, 0) yield from dut.master.write(0x6000_0000//adr_div, 0)
yield from dut.master.write(0x0002_0000//adr_div, 0) yield from dut.master.write(0x6001_0000//adr_div, 0)
yield from dut.master.write(0x6001_0040//adr_div, 0)
def checker(dut): def checker(dut):
yield dut.slave.ack.eq(1) yield dut.slave.ack.eq(1)
while (yield dut.slave.stb) == 0: while (yield dut.slave.stb) == 0:
yield yield
self.assertEqual((yield dut.slave.adr), 0x1000_0000//adr_div) self.assertEqual((yield dut.slave.adr), 0xf000_0000//adr_div)
yield yield
self.assertEqual((yield dut.slave.adr), 0x0003_0000//adr_div) self.assertEqual((yield dut.slave.adr), 0x8100_0000//adr_div)
yield
self.assertEqual((yield dut.slave.adr), 0x2000_0000//adr_div)
yield yield
for i in range(128): for i in range(128):
yield yield
@ -293,13 +296,17 @@ class TestWishbone(unittest.TestCase):
self.master = wishbone.Interface(data_width=32, address_width=32, addressing=addressing) self.master = wishbone.Interface(data_width=32, address_width=32, addressing=addressing)
self.slave = wishbone.Interface(data_width=32, address_width=32, addressing=addressing) self.slave = wishbone.Interface(data_width=32, address_width=32, addressing=addressing)
self.remapper = wishbone.Remapper(self.master, self.slave, self.remapper = wishbone.Remapper(self.master, self.slave,
origin = 0x1_0000, origin = 0x0000_0000,
size = 0x8_0000, size = 0x2000_0000,
src_regions = [ src_regions = [
SoCRegion(origin=0x0001_0000, size=0x1_0000), SoCRegion(origin=0x0000_0000, size=65536),
SoCRegion(origin=0x0001_0000, size=64),
SoCRegion(origin=0x0001_0040, size=8),
], ],
dst_regions = [ dst_regions = [
SoCRegion(origin=0x1000_0000, size=0x1_0000), SoCRegion(origin=0xf000_0000, size=65536),
SoCRegion(origin=0x8100_0000, size=64),
SoCRegion(origin=0x2000_0000, size=8),
] ]
) )
dut = DUT() dut = DUT()