litex/gen: add io with SDRInput/SDROutput (if not overrided, register is supposed to be infered).
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from migen.fhdl.specials import Special
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class InferedSDRIO(Module):
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def __init__(self, i, o, clk, clk_domain):
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if clk_domain is None:
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raise NotImplementedError("Attempted to use an InferedSDRIO but no clk_domain specified.")
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sync = getattr(self.sync, clk_domain)
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sync += o.eq(i)
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class SDRIO(Special):
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def __init__(self, i, o, clk=ClockSignal()):
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assert len(i) == len(o)
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Special.__init__(self)
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print(o)
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self.i = wrap(i)
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self.o = wrap(o)
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self.clk = wrap(clk)
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self.clk_domain = None if not hasattr(clk, "cd") else clk.cd
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def iter_expressions(self):
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yield self, "i", SPECIAL_INPUT
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yield self, "o", SPECIAL_OUTPUT
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yield self, "clk", SPECIAL_INPUT
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@staticmethod
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def lower(dr):
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return InferedSDRIO(dr.i, dr.o, dr.clk, dr.clk_domain)
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class SDRInput(SDRIO): pass
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class SDROutput(SDRIO): pass
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