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[fix] Trion T8 have a V1 PLL in BGA packages, but a V2 PLL in TQFP package. DP files varies accordingly

This commit is contained in:
Charles-Henri Mousset 2024-04-15 09:29:48 +02:00
parent 2d1dd45fd2
commit 739b66a15b
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2 changed files with 3 additions and 3 deletions
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4
litex/build/efinix/dbparser.py
View File

@ -107,9 +107,9 @@ class EfinixDbParser:
peri = root.findall('efxpt:periphery_instance', namespaces)
for p in peri:
# T20/T120 have instance attribute in single_conn
# not true for T4/T8 -> search in dependency subnode
# not true for T4/T8 (except for TQFP144 package) -> search in dependency subnode
if p.get('block') == 'pll':
if self.device[0:2] not in ['T4', 'T8']:
if self.device[0:2] not in ['T4', 'T8'] or self.device[0:6] == "T8Q144":
conn = p.findall('efxpt:single_conn', namespaces)
for c in conn:
i = c.get('instance')

2
litex/build/efinix/ifacewriter.py
View File

@ -289,7 +289,7 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True)
elif block["input_clock"] == "EXTERNAL":
# PLL V1 has a different configuration
if partnumber[0:2] in ["T4", "T8"]:
if partnumber[0:2] in ["T4", "T8"] and partnumber != "T8Q144":
cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_res="{}", refclk_name="{}", ext_refclk_no="{}")\n\n' \
.format(name, block["resource"], block["input_clock_pad"], block["input_clock_name"], block["clock_no"])
else: