tools/litex_sim: Add pre-definied commented config flags.
This commit is contained in:
parent
7028745829
commit
73c76c6126
|
@ -161,13 +161,20 @@ class SimSoC(SoCCore):
|
||||||
platform = Platform()
|
platform = Platform()
|
||||||
sys_clk_freq = int(1e6)
|
sys_clk_freq = int(1e6)
|
||||||
|
|
||||||
|
# CRG --------------------------------------------------------------------------------------
|
||||||
|
self.submodules.crg = CRG(platform.request("sys_clk"))
|
||||||
|
|
||||||
# SoCCore ----------------------------------------------------------------------------------
|
# SoCCore ----------------------------------------------------------------------------------
|
||||||
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
|
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
|
||||||
ident = "LiteX Simulation",
|
ident = "LiteX Simulation",
|
||||||
**kwargs)
|
**kwargs)
|
||||||
|
|
||||||
# CRG --------------------------------------------------------------------------------------
|
# BIOS Config ------------------------------------------------------------------------------
|
||||||
self.submodules.crg = CRG(platform.request("sys_clk"))
|
# FIXME: Expose?
|
||||||
|
#self.add_config("BIOS_NO_PROMPT")
|
||||||
|
#self.add_config("BIOS_NO_DELAYS")
|
||||||
|
#self.add_config("BIOS_NO_BUILD_TIME")
|
||||||
|
#self.add_config("BIOS_NO_CRC")
|
||||||
|
|
||||||
# SDRAM ------------------------------------------------------------------------------------
|
# SDRAM ------------------------------------------------------------------------------------
|
||||||
if not self.integrated_main_ram_size and with_sdram:
|
if not self.integrated_main_ram_size and with_sdram:
|
||||||
|
|
Loading…
Reference in New Issue