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CHANGES: Update.

This commit is contained in:
Florent Kermarrec 2023-07-27 13:58:45 +02:00
parent bbf944c3ba
commit 74401d6f03
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@ -13,6 +13,7 @@
- LiteXModule/CSR : Fixed CSR collection order causing CSR clock domain to be changed.
- litepcie/US(P) : Fixed root cause of possible MSI deadlock.
- soc/add_uart : Fixed stub behavior (sink/source swap).
- build/efinix : Fixed AsyncFIFO issues (Minimum of 2 buffer stages).
[> Added
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@ -49,6 +50,7 @@
- soc/add_uartbone/sata/sdcard : Added support for multiple instances in gateware as for the other cores.
- liteeth_gen : Added raw UDP port support.
- build/vivado : Added .dcp generation also after synthesis and placement.
- gen: : Added initial LiteXContext to easily get build properties (platform, device, toolchain, etc...)
[> Changed
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