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soc/integration/soc_core: allow user to defined internal csr/interrupts 

For some designs with different capabilities, we want to run the same software
and then have the CSRs/Interrupts defined to a specific location.
This commit is contained in:
Florent Kermarrec 2019-05-10 11:05:34 +02:00
parent f333abcfcb
commit 7445b9e2e0
1 changed files with 22 additions and 16 deletions
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34
litex/soc/integration/soc_core.py
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@ -248,9 +248,13 @@ class SoCCore(Module):
self.soc_csr_map = {} self.soc_csr_map = {}
self.soc_interrupt_map = {} self.soc_interrupt_map = {}
# add user csrs
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
if with_ctrl: if with_ctrl:
self.submodules.ctrl = SoCController() self.submodules.ctrl = SoCController()
self.add_csr("ctrl") self.add_csr("ctrl", allow_user_defined=True)
if cpu_type is not None: if cpu_type is not None:
if cpu_type == "lm32": if cpu_type == "lm32":
@ -267,7 +271,7 @@ class SoCCore(Module):
self.add_cpu(minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant)) self.add_cpu(minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant))
else: else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type)) raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_csr("cpu") self.add_csr("cpu", allow_user_defined=True)
self.add_wb_master(self.cpu.ibus) self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus) self.add_wb_master(self.cpu.dbus)
if with_ctrl: if with_ctrl:
@ -280,10 +284,6 @@ class SoCCore(Module):
for _name, _id in self.interrupt_map.items(): for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id) self.add_interrupt(_name, _id)
# add user csrs
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
self.config["CPU_TYPE"] = str(cpu_type).upper() self.config["CPU_TYPE"] = str(cpu_type).upper()
if self.cpu_variant: if self.cpu_variant:
self.config["CPU_VARIANT"] = str(cpu_type).upper() self.config["CPU_VARIANT"] = str(cpu_type).upper()
@ -313,22 +313,22 @@ class SoCCore(Module):
else: else:
self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate) self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy)) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.add_csr("uart_phy") self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart") self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart") self.add_interrupt("uart", allow_user_defined=True)
if ident: if ident:
if ident_version: if ident_version:
ident = ident + " " + version() ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident) self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem") self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq) self.config["CLOCK_FREQUENCY"] = int(clk_freq)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq)) self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer: if with_timer:
self.submodules.timer0 = timer.Timer() self.submodules.timer0 = timer.Timer()
self.add_csr("timer0") self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0") self.add_interrupt("timer0", allow_user_defined=True)
def add_cpu(self, cpu): def add_cpu(self, cpu):
if self.finalized: if self.finalized:
@ -342,9 +342,12 @@ class SoCCore(Module):
self.add_cpu(cpu_or_bridge) self.add_cpu(cpu_or_bridge)
self.cpu_or_bridge = self.cpu self.cpu_or_bridge = self.cpu
def add_interrupt(self, interrupt_name, interrupt_id=None): def add_interrupt(self, interrupt_name, interrupt_id=None, allow_user_defined=False):
# check that interrupt_name is not already used # check that interrupt_name is not already used
if interrupt_name in self.soc_interrupt_map.keys(): if interrupt_name in self.soc_interrupt_map.keys():
if allow_user_defined:
return
else:
raise ValueError("Interrupt conflit, {} name already used".format(interrupt_name)) raise ValueError("Interrupt conflit, {} name already used".format(interrupt_name))
# check that interrupt_id is in range # check that interrupt_id is in range
@ -367,9 +370,12 @@ class SoCCore(Module):
interrupt_id, _name)) interrupt_id, _name))
self.soc_interrupt_map.update({interrupt_name: interrupt_id}) self.soc_interrupt_map.update({interrupt_name: interrupt_id})
def add_csr(self, csr_name, csr_id=None): def add_csr(self, csr_name, csr_id=None, allow_user_defined=False):
# check that csr_name is not already used # check that csr_name is not already used
if csr_name in self.soc_csr_map.keys(): if csr_name in self.soc_csr_map.keys():
if allow_user_defined:
return
else:
raise ValueError("CSR conflit, {} name already used".format(csr_name)) raise ValueError("CSR conflit, {} name already used".format(csr_name))
# check that csr_id is in range # check that csr_id is in range