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cores/liteeth_mini: adapt all phys to new migen

This commit is contained in:
Florent Kermarrec 2015-10-23 20:29:04 +02:00
parent 197e5cf31c
commit 7459419ab4
3 changed files with 6 additions and 12 deletions
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10
misoc/cores/liteeth_mini/phy/gmii.py
View File

@ -92,11 +92,7 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
class LiteEthPHYGMII(Module, AutoCSR): class LiteEthPHYGMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True): def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8 self.dw = 8
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
pads, self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
with_hw_init_reset) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
"eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
"eth_rx")
self.sink, self.source = self.tx.sink, self.rx.source self.sink, self.source = self.tx.sink, self.rx.source

4
misoc/cores/liteeth_mini/phy/mii.py
View File

@ -105,6 +105,6 @@ class LiteEthPHYMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True): def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8 self.dw = 8
self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset) self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx") self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx") self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source self.sink, self.source = self.tx.sink, self.rx.source

4
misoc/cores/liteeth_mini/phy/s6rgmii.py
View File

@ -155,9 +155,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
class LiteEthPHYRGMII(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True): def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8 self.dw = 8
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
pads,
with_hw_init_reset)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source self.sink, self.source = self.tx.sink, self.rx.source