cores/liteeth_mini: adapt all phys to new migen
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@ -92,11 +92,7 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
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class LiteEthPHYGMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
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pads,
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with_hw_init_reset)
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self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
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"eth_tx")
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self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
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"eth_rx")
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self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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@ -105,6 +105,6 @@ class LiteEthPHYMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
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self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx")
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self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx")
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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@ -155,9 +155,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
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class LiteEthPHYRGMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads,
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pads,
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with_hw_init_reset)
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self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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