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boards: add initial NeTV2 support (clocks, leds, dram, ethernet)

This commit is contained in:
Florent Kermarrec 2019-05-10 18:55:40 +02:00
parent a49d170a6d
commit 745d83a332
3 changed files with 221 additions and 1 deletions
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100
litex/boards/platforms/netv2.py Normal file
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@ -0,0 +1,100 @@
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clock
("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
# leds
("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("AA21"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")),
# flash
("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("vpp", Pins("P21")),
Subsignal("hold", Pins("R21")),
IOStandard("LVCMOS33")
),
# serial
("serial", 0,
Subsignal("tx", Pins("E14")),
Subsignal("rx", Pins("E13")),
IOStandard("LVCMOS33"),
),
# dram
("ddram", 0,
Subsignal("a", Pins(
"U6 V4 W5 V5 AA1 Y2 AB1 AB3",
"AB2 Y3 W6 Y1 V2 AA3"
),
IOStandard("SSTL15")),
Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("V8"), IOStandard("SSTL15")),
Subsignal("dm", Pins("M5 L3"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"N2 M6 P1 N5 P2 N4 R1 P6 "
"K3 M2 K4 M3 J6 L5 J4 K6 "
),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("P5 M1"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("P4 L1"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("Y8"), IOStandard("SSTL15")),
Subsignal("odt", Pins("W9"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
# ethernet
("eth_clocks", 0,
Subsignal("ref_clk", Pins("D17")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("F16")),
Subsignal("rx_data", Pins("A20 B18")),
Subsignal("crs_dv", Pins("C20")),
Subsignal("tx_en", Pins("A19")),
Subsignal("tx_data", Pins("C18 C19")),
Subsignal("mdc", Pins("F14")),
Subsignal("mdio", Pins("F13")),
Subsignal("rx_er", Pins("B20")),
Subsignal("int_n", Pins("D21")),
IOStandard("LVCMOS33")
),
# sdcard
("sdcard", 0,
Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")),
Subsignal("cmd", Pins("L13"), Misc("PULLUP True")),
Subsignal("clk", Pins("K18")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 20.0
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")

114
litex/boards/targets/netv2.py Normal file
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@ -0,0 +1,114 @@
#!/usr/bin/env python3
import argparse
from migen import *
from litex.boards.platforms import netv2
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT41J128M16
from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII
from liteeth.core.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk50"), 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 50e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = netv2.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# sdram
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()

8
test/test_targets.py
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@ -41,6 +41,11 @@ class TestTargets(unittest.TestCase):
errors = build_test([BaseSoC(), EthernetSoC()])
self.assertEqual(errors, 0)
def test_netv2(self):
from litex.boards.targets.netv2 import BaseSoC, EthernetSoC
errors = build_test([BaseSoC(), EthernetSoC()])
self.assertEqual(errors, 0)
def test_nexys4ddr(self):
from litex.boards.targets.nexys4ddr import BaseSoC
errors = build_test([BaseSoC()])
@ -85,7 +90,8 @@ class TestTargets(unittest.TestCase):
platforms = []
# Xilinx
platforms += ["minispartan6", "sp605"] # Spartan6
platforms += ["arty", "nexys4ddr", "nexys_video", "ac701"] # Artix7
platforms += ["arty", "netv2", "nexys4ddr", "nexys_video", # Artix7
"ac701"]
platforms += ["kc705", "genesys2"] # Kintex7
platforms += ["kcu105"] # Kintex Ultrascale