soc/integration/soc_core: add new parameters --with-uartbone and --with-jtagbone, deprecate crossover+uartbone

- `--with-jtagbone` and `--with-uartbone` are now integrated in SoCCore
  arguments. This class also handle `add_jtagbone` and `add_uartbone`
- when a target try to add one of this option a warning is displayed and
  insertion is bypassed
- `crossover+uartbone` is deprecated -> `--uart-name=crossover
  --with-uartbone`
- jtag capability ((un)supported) is now handled at platform level

litex/build/anlogic/platform.py

@@ -13,7 +13,8 @@ from litex.build.anlogic import common, anlogic
 # AnlogicPlatform ----------------------------------------------------------------------------------
 
 class AnlogicPlatform(GenericPlatform):
-    _bitstream_ext = ".bit"
+    _bitstream_ext  = ".bit"
+    _jtag_support  = False
 
     _supported_toolchains = ["td"]
 

litex/build/colognechip/platform.py

@@ -13,6 +13,7 @@ from litex.build.colognechip import common, colognechip
 
 class CologneChipPlatform(GenericPlatform):
     bitstream_ext = "_00.cfg.bit"
+    _jtag_support = False
 
     _supported_toolchains = ["colognechip"]
 

litex/build/generic_platform.py

@@ -329,6 +329,7 @@ class ConstraintManager:
 
 class GenericPlatform:
     device_family  = None
+    _jtag_support  = True # JTAGBone can't be used with all FPGAs.
     _bitstream_ext = None # None by default, overridden by vendor platform, may
                           # be a string when same extension is used for sram and
                           # flash. A dict must be provided otherwise
@@ -504,6 +505,16 @@ class GenericPlatform:
     def create_programmer(self):
         raise NotImplementedError
 
+    @property
+    def jtag_support(self):
+        if isinstance(self._jtag_support, str):
+            return self._jtag_support
+        else:
+            for dev in self._jtag_support:
+                if self.device.startswith(dev):
+                    return True
+            return False
+
     @property
     def support_mixed_language(self):
         return self.toolchain.support_mixed_language

litex/build/gowin/platform.py

@@ -14,6 +14,7 @@ from litex.build.gowin import common, gowin
 
 class GowinPlatform(GenericPlatform):
     _bitstream_ext = ".fs"
+    _jtag_support  = False
 
     _supported_toolchains = ["gowin", "apicula"]
 

litex/build/microsemi/platform.py

@@ -11,6 +11,7 @@ from litex.build.microsemi import common, libero_soc
 
 class MicrosemiPlatform(GenericPlatform):
     _bitstream_ext = ".bit"
+    _jtag_support  = False
 
     _supported_toolchains = ["libero_soc_polarfire"]
 

litex/build/parser.py

@@ -9,11 +9,14 @@ import sys
 import logging
 import argparse
 import importlib
+import time
 
 from litex.soc.cores import cpu
 from litex.soc.integration import soc_core
 from litex.soc.integration import builder
 
+from litex.gen.common import *
+
 # Litex Argument Parser ----------------------------------------------------------------------------
 
 class LiteXArgumentParser(argparse.ArgumentParser):
@@ -63,6 +66,9 @@ class LiteXArgumentParser(argparse.ArgumentParser):
             self.set_platform(platform)
             self.add_target_group()
         self.add_logging_group()
+        # workaround for backward compatibility
+        self._rm_jtagbone = False
+        self._rm_uartbone = False
 
     def set_platform(self, platform):
         """ set platform. Check first if not already set
@@ -104,8 +110,21 @@ class LiteXArgumentParser(argparse.ArgumentParser):
         """ wrapper to add argument to "Target options group" from outer of this
         class
         """
+        arg = args[0]
+        if arg in ["--with-jtagbone", "--with-uartbone"]:
+            if arg == "--with-jtagbone":
+                self._rm_jtagbone = True
+            else:
+                self._rm_uartbone = True
+            print("Warning {} {} {}".format(
+                colorer(arg, color="red"),
+                colorer(" is added by SoCCore. ", color="red"),
+                colorer("Please remove this option from target", color="yellow")))
+            time.sleep(2)
+            return # bypass insert
         if self._target_group is None:
             self._target_group = self.add_argument_group(title="Target options")
+
         self._target_group.add_argument(*args, **kwargs)
 
     def add_logging_group(self):
@@ -147,7 +166,14 @@ class LiteXArgumentParser(argparse.ArgumentParser):
         ======
         soc_core arguments dict
         """
-        return soc_core.soc_core_argdict(self._args) # FIXME: Rename to soc_argdict in the future.
+        soc_arg = soc_core.soc_core_argdict(self._args) # FIXME: Rename to soc_argdict in the future.
+
+        # Work around for backward compatibility
+        if self._rm_jtagbone:
+            soc_arg.pop("with_jtagbone")
+        if self._rm_uartbone:
+            soc_arg.pop("with_uartbone")
+        return soc_arg
 
     @property
     def toolchain_argdict(self):

litex/build/quicklogic/platform.py

@@ -13,6 +13,7 @@ from litex.build.quicklogic import common, f4pga
 
 class QuickLogicPlatform(GenericPlatform):
     _bitstream_ext = ".bit"
+    _jtag_support  = False
 
     _supported_toolchains = ["f4pga"]
 

litex/build/xilinx/platform.py

@@ -26,6 +26,12 @@ class XilinxPlatform(GenericPlatform):
         "ultrascale+" : ["vivado"],
     }
 
+    _jtag_support = [
+        "xc6",
+        "xc7a", "xc7k", "xc7v", "xc7z",
+        "xcau", "xcku", "xcvu", "xczu"
+    ]
+
     def __init__(self, *args, toolchain="ise", **kwargs):
         GenericPlatform.__init__(self, *args, **kwargs)
         self.edifs = set()
@@ -126,6 +132,7 @@ class XilinxPlatform(GenericPlatform):
         else:
             return dict()
 
+
 # XilinxSpartan6Platform ---------------------------------------------------------------------------
 
 class XilinxSpartan6Platform(XilinxPlatform):

litex/soc/integration/soc_core.py

@@ -108,6 +108,13 @@ class SoCCore(LiteXSoC):
         # Controller parameters
         with_ctrl                = True,
 
+        # JTAGBone
+        with_jtagbone            = False,
+        jtagbone_chain           = 1,
+
+        # UARTBone
+        with_uartbone            = False,
+
         # Others
         **kwargs):
 
@@ -174,6 +181,31 @@ class SoCCore(LiteXSoC):
         # Wishbone Slaves.
         self.wb_slaves = {}
 
+        # Parameters check validity ----------------------------------------------------------------
+
+        # Check if jtagbone is supported (SPI only device or no user access).
+        if with_jtagbone:
+            if not platform.jtag_support:
+                self.logger.error("{} {} with {} FPGA".format(
+                    colorer("JTAGBone isn't supported for platform", color="red"),
+                    platform.name, platform.device))
+                raise SoCError()
+        if with_uart:
+            # crossover+uartbone is kept as backward compatibility
+            if uart_name == "crossover+uartbone":
+                self.logger.warning("{} UART: is deprecated {}".format(
+                    colorer(uart_name, color="yellow"),
+                    colorer("please use --uart-name=\"crossover\" --with-uartbone", color="red")))
+                time.sleep(2)
+                # Already configured.
+                self._uartbone = True
+                uart_name      = "crossover"
+
+            # JTAGBone and jtag_uart can't be used at the same time.
+            assert not (with_jtagbone and uart_name == "jtag_uart")
+            # UARTBone and serial can't be used at the same time.
+            assert not (with_uartbone and uart_name == "serial")
+
         # Modules instances ------------------------------------------------------------------------
 
         # Add SoCController
@@ -220,10 +252,18 @@ class SoCCore(LiteXSoC):
         if ident != "":
             self.add_identifier("identifier", identifier=ident, with_build_time=ident_version)
 
+        # Add UARTBone
+        if with_uartbone:
+            self.add_uartbone(baudrate=uart_baudrate)
+
         # Add UART
         if with_uart:
             self.add_uart(name="uart", uart_name=uart_name, baudrate=uart_baudrate, fifo_depth=uart_fifo_depth)
 
+        # Add JTAGBone
+        if with_jtagbone:
+            self.add_jtagbone(chain=jtagbone_chain)
+
         # Add Timer
         if with_timer:
             self.add_timer(name="timer0")
@@ -294,6 +334,13 @@ def soc_core_args(parser):
     soc_group.add_argument("--uart-baudrate",   default=115200,      type=auto_int, help="UART baudrate.")
     soc_group.add_argument("--uart-fifo-depth", default=16,          type=auto_int, help="UART FIFO depth.")
 
+    # UARTBone parameters
+    soc_group.add_argument("--with-uartbone",   action="store_true",                help="Enable UARTbone.")
+
+    # JTAGBone parameters
+    soc_group.add_argument("--with-jtagbone",  action="store_true", help="Enable Jtagbone support.")
+    soc_group.add_argument("--jtagbone-chain", default=1, type=int, help="Jtagbone chain index.")
+
     # Timer parameters
     soc_group.add_argument("--no-timer",        action="store_true", help="Disable Timer.")
     soc_group.add_argument("--timer-uptime",    action="store_true", help="Add an uptime capability to Timer.")