Merge pull request #965 from thirtythreeforty/ecp5-pll-x4
ECP5PLL: implement 4-output solver
This commit is contained in:
enjoy-digital
GitHub
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751e99690e
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@ -2,6 +2,7 @@
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# This file is part of LiteX.
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#
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# Copyright (c) 2018-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 George Hilliard <thirtythreeforty@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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@ -12,21 +13,24 @@ from litex.soc.cores.clock.common import *
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# Lattice / ECP5 -----------------------------------------------------------------------------------
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class ECP5PLL(Module):
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nclkouts_max = 3
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nclkouts_max = 4
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clki_div_range = (1, 128+1)
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clkfb_div_range = (1, 128+1)
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clko_div_range = (1, 128+1)
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clki_freq_range = ( 8e6, 400e6)
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clko_freq_range = (3.125e6, 400e6)
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vco_freq_range = ( 400e6, 800e6)
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pfd_freq_range = ( 10e6, 400e6)
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def __init__(self):
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self.logger = logging.getLogger("ECP5PLL")
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self.logger.info("Creating ECP5PLL.")
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self.reset = Signal()
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self.locked = Signal()
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self.stdby = Signal()
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self.clkin_freq = None
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self.vcxo_freq = None
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self.dpa_en = False
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self.nclkouts = 0
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self.clkouts = {}
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self.config = {}
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@ -44,13 +48,13 @@ class ECP5PLL(Module):
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self.clkin_freq = freq
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register_clkin_log(self.logger, clkin, freq)
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def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True):
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def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True, uses_dpa=True):
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(clko_freq_min, clko_freq_max) = self.clko_freq_range
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assert freq >= clko_freq_min
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assert freq <= clko_freq_max
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assert self.nclkouts < self.nclkouts_max
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clkout = Signal()
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self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
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self.clkouts[self.nclkouts] = (clkout, freq, phase, margin, uses_dpa)
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if with_reset:
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self.specials += AsyncResetSynchronizer(cd, ~self.locked)
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self.comb += cd.clk.eq(clkout)
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@ -59,35 +63,76 @@ class ECP5PLL(Module):
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def compute_config(self):
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config = {}
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def in_range(n, r):
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(r_min, r_max) = r
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return n >= r_min and n <= r_max
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def found_clk(n, f, d, p):
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config["clko{}_freq".format(n)] = f
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config["clko{}_div".format(n)] = d
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config["clko{}_phase".format(n)] = p
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for clki_div in range(*self.clki_div_range):
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if not in_range(self.clkin_freq / clki_div, self.pfd_freq_range):
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continue
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config["clki_div"] = clki_div
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for clkfb_div in range(*self.clkfb_div_range):
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all_valid = True
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vco_freq = self.clkin_freq/clki_div*clkfb_div*1 # clkos3_div=1
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max:
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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valid = False
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for d in range(*self.clko_div_range):
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clk_freq = vco_freq/d
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if abs(clk_freq - f) <= f*m:
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config["clko{}_freq".format(n)] = clk_freq
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config["clko{}_div".format(n)] = d
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config["clko{}_phase".format(n)] = p
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valid = True
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break
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if not valid:
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all_valid = False
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# pick a suitable feedback clock
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found_fb = None
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for n, (clk, f, p, m, dpa) in sorted(self.clkouts.items()):
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if dpa and self.dpa_en:
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# cannot use clocks whose phase the user will change
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continue
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for d in range(*self.clko_div_range):
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vco_freq = self.clkin_freq/clki_div*clkfb_div*d
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clk_freq = vco_freq/d
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if in_range(vco_freq, self.vco_freq_range) \
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and abs(clk_freq - f) <= f*m:
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found_fb = n
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found_clk(n, f, d, p)
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break
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if found_fb is not None:
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break
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else:
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all_valid = False
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# none found, try to use a new output
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for d in range(*self.clko_div_range):
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vco_freq = self.clkin_freq/clki_div*clkfb_div*d
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clk_freq = vco_freq/d
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if self.nclkouts < self.nclkouts_max \
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and in_range(vco_freq, self.vco_freq_range) \
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and in_range(clk_freq, self.clko_freq_range):
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found_fb = self.nclkouts
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found_clk(found_fb, clk_freq, d, 0)
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break
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else:
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continue
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# vco_freq is known, compute remaining clocks' output settings
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all_valid = True
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for n, (clk, f, p, m, dpa) in sorted(self.clkouts.items()):
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if n == found_fb:
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continue # already picked this one
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for d in range(*self.clko_div_range):
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clk_freq = vco_freq/d
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if abs(clk_freq - f) <= f*m:
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found_clk(n, f, d, p)
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break
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else:
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all_valid = False
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if all_valid:
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if found_fb > self.nclkouts:
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self.create_clkout(ClockDomain('feedback'), vco_freq / clkfb_div)
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config["vco"] = vco_freq
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config["clkfb"] = found_fb
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config["clkfb_div"] = clkfb_div
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compute_config_log(self.logger, config)
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return config
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raise ValueError("No PLL config found")
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def expose_dpa(self):
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self.dpa_en = True
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self.phase_sel = Signal(2)
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self.phase_dir = Signal()
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self.phase_step = Signal()
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@ -106,8 +151,8 @@ class ECP5PLL(Module):
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def do_finalize(self):
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config = self.compute_config()
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clkfb = Signal()
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locked = Signal()
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n_to_l = {0: "P", 1: "S", 2: "S2", 3: "S3"}
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self.params.update(
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attr=[
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("FREQUENCY_PIN_CLKI", str(self.clkin_freq/1e6)),
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@ -117,18 +162,14 @@ class ECP5PLL(Module):
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("MFG_GMCREF_SEL", "2")],
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i_RST = self.reset,
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i_CLKI = self.clkin,
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i_STDBY = self.stdby,
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o_LOCK = locked,
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p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for feedback with div=1.
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p_CLKOS3_ENABLE = "ENABLED",
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p_CLKOS3_DIV = 1,
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p_CLKOS3_FPHASE = 0,
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p_CLKOS3_CPHASE = 23,
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p_FEEDBK_PATH = "INT_O{}".format(n_to_l[config['clkfb']]),
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p_CLKFB_DIV = config["clkfb_div"],
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p_CLKI_DIV = config["clki_div"]
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)
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self.comb += self.locked.eq(locked & ~self.reset)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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n_to_l = {0: "P", 1: "S", 2: "S2"}
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for n, (clk, f, p, m, dpa) in sorted(self.clkouts.items()):
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div = config["clko{}_div".format(n)]
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cphase = int(p*(div + 1)/360 + div - 1)
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self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
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@ -117,7 +117,8 @@ class TestClock(unittest.TestCase):
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pll = ECP5PLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6, uses_dpa=(i != 0))
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pll.expose_dpa()
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pll.compute_config()
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# Lattice / NX
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