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Merge pull request #1941 from motec-research/vexriscv_debug_halted 

cpu/vexriscv: expose o_halted
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enjoy-digital 2024-04-26 13:43:40 +02:00 committed by GitHub
parent 7aae2bf897 3a008b4988
commit 76a704377f
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1 changed files with 3 additions and 1 deletions
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litex/soc/cores/cpu/vexriscv/core.py
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@ -210,6 +210,7 @@ class VexRiscv(CPU, AutoCSR):
self.o_cmd_ready = Signal()
self.o_rsp_data = Signal(32)
self.o_resetOut = Signal()
self.o_halted = Signal()
reset_debug_logic = Signal()
@ -278,7 +279,8 @@ class VexRiscv(CPU, AutoCSR):
i_debug_bus_cmd_payload_data = self.i_cmd_payload_data,
o_debug_bus_cmd_ready = self.o_cmd_ready,
o_debug_bus_rsp_data = self.o_rsp_data,
o_debug_resetOut = self.o_resetOut
o_debug_resetOut = self.o_resetOut,
o_halted = self.o_halted,
)
def add_cfu(self, cfu_filename):