Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

vexiiriscv: have opensbi behind a option 

this way opensbi things are only activated,
when a linux variant is used.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit is contained in:
Fin Maaß 2024-10-18 07:58:44 +02:00
parent bc3e90c93a
commit 773fb34079
No known key found for this signature in database
1 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex/soc/cores/cpu/vexiiriscv/core.py
View File

@ -57,6 +57,7 @@ class VexiiRiscv(CPU):
with_rva = False with_rva = False
with_dma = False with_dma = False
with_axi3 = False with_axi3 = False
with_opensbi = False
jtag_tap = False jtag_tap = False
jtag_instruction = False jtag_instruction = False
with_cpu_clk = False with_cpu_clk = False
@ -163,6 +164,7 @@ class VexiiRiscv(CPU):
VexiiRiscv.vexii_args += " --relaxed-branch" VexiiRiscv.vexii_args += " --relaxed-branch"
if args.cpu_variant in ["linux", "debian"]: if args.cpu_variant in ["linux", "debian"]:
VexiiRiscv.with_opensbi = True
VexiiRiscv.vexii_args += " --with-rva --with-supervisor" VexiiRiscv.vexii_args += " --with-rva --with-supervisor"
VexiiRiscv.vexii_args += " --fetch-l1-ways=4 --fetch-l1-mem-data-width-min=64" VexiiRiscv.vexii_args += " --fetch-l1-ways=4 --fetch-l1-mem-data-width-min=64"
VexiiRiscv.vexii_args += " --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64" VexiiRiscv.vexii_args += " --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64"
@ -366,6 +368,7 @@ class VexiiRiscv(CPU):
md5_hash.update(str(VexiiRiscv.memory_regions).encode('utf-8')) md5_hash.update(str(VexiiRiscv.memory_regions).encode('utf-8'))
md5_hash.update(str(VexiiRiscv.vexii_args).encode('utf-8')) md5_hash.update(str(VexiiRiscv.vexii_args).encode('utf-8'))
md5_hash.update(str(VexiiRiscv.vexii_video).encode('utf-8')) md5_hash.update(str(VexiiRiscv.vexii_video).encode('utf-8'))
md5_hash.update(str(VexiiRiscv.with_opensbi).encode('utf-8'))
# md5_hash.update(str(VexiiRiscv.internal_bus_width).encode('utf-8')) # md5_hash.update(str(VexiiRiscv.internal_bus_width).encode('utf-8'))
@ -442,6 +445,7 @@ class VexiiRiscv(CPU):
# Set Human-name. # Set Human-name.
self.human_name = f"{self.human_name} {self.xlen}-bit" self.human_name = f"{self.human_name} {self.xlen}-bit"
if VexiiRiscv.with_opensbi:
# Set UART/Timer0 CSRs to the ones used by OpenSBI. # Set UART/Timer0 CSRs to the ones used by OpenSBI.
soc.csr.add("uart", n=2) soc.csr.add("uart", n=2)
soc.csr.add("timer0", n=3) soc.csr.add("timer0", n=3)