soc/cores/uart: add uart multiplexer
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@ -8,6 +8,12 @@ from litex.soc.interconnect import stream
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from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
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from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
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class RS232PHYInterface:
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def __init__(self):
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self.sink = stream.Endpoint([("data", 8)])
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self.source = stream.Endpoint([("data", 8)])
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class RS232PHYRX(Module):
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class RS232PHYRX(Module):
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def __init__(self, pads, tuning_word):
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def __init__(self, pads, tuning_word):
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self.source = stream.Endpoint([("data", 8)])
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self.source = stream.Endpoint([("data", 8)])
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@ -183,3 +189,21 @@ class UARTWishboneBridge(WishboneStreamingBridge):
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def __init__(self, pads, clk_freq, baudrate=115200):
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def __init__(self, pads, clk_freq, baudrate=115200):
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self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)
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self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)
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WishboneStreamingBridge.__init__(self, self.phy, clk_freq)
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WishboneStreamingBridge.__init__(self, self.phy, clk_freq)
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class UARTMultiplexer(Module):
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def __init__(self, uarts, phy):
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self.sel = Signal(max=len(uarts))
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# # #
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cases = {}
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for n in range(len(uarts)):
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# don't stall uarts when not selected
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self.comb += uarts[n].sink.ready.eq(1)
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# connect core to phy
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cases[n] = [
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phy.source.connect(uarts[n].source),
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uarts[n].sink.connect(phy.sink)
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]
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self.comb += Case(self.sel, cases)
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