sdramphy/gensdrphy: fix rddata_en generation
This commit is contained in:
parent
a2c7ff4c0c
commit
777ebb7875
|
@ -72,7 +72,8 @@ class GENSDRPHY(Module):
|
||||||
drive_dq = Signal()
|
drive_dq = Signal()
|
||||||
self.sync += sd_dq_out.eq(self.dfi.p0.wrdata),
|
self.sync += sd_dq_out.eq(self.dfi.p0.wrdata),
|
||||||
self.specials += Tristate(pads.dq, sd_dq_out, drive_dq)
|
self.specials += Tristate(pads.dq, sd_dq_out, drive_dq)
|
||||||
self.sync += If(self.dfi.p0.wrdata_en,
|
self.sync += \
|
||||||
|
If(self.dfi.p0.wrdata_en,
|
||||||
pads.dm.eq(self.dfi.p0.wrdata_mask)
|
pads.dm.eq(self.dfi.p0.wrdata_mask)
|
||||||
).Else(
|
).Else(
|
||||||
pads.dm.eq(0)
|
pads.dm.eq(0)
|
||||||
|
@ -89,5 +90,5 @@ class GENSDRPHY(Module):
|
||||||
self.comb += drive_dq.eq(d_dfi_wrdata_en)
|
self.comb += drive_dq.eq(d_dfi_wrdata_en)
|
||||||
|
|
||||||
rddata_sr = Signal(4)
|
rddata_sr = Signal(4)
|
||||||
self.comb += self.dfi.p0.rddata_valid.eq(rddata_sr[0])
|
self.comb += self.dfi.p0.rddata_valid.eq(rddata_sr[3])
|
||||||
self.sync += rddata_sr.eq(Cat(self.dfi.p0.rddata_en, rddata_sr[1:]))
|
self.sync += rddata_sr.eq(Cat(self.dfi.p0.rddata_en, rddata_sr[:3]))
|
||||||
|
|
Loading…
Reference in New Issue