Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

realign rxdata / rxcharisk directly in gtx

Browse source
This commit is contained in:
Florent Kermarrec 2014-09-24 12:13:43 +02:00
parent f74471d027
commit 7790105913
1 changed files with 25 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

29
lib/sata/k7sataphy/gtx.py
View file

@ -27,7 +27,6 @@ class GTXE2_CHANNEL(Module):
self.rxuserrdy = Signal()
# Receive Ports - 8b10b Decoder
self.rxchariscomma = Signal(2)
self.rxcharisk = Signal(2)
self.rxdisperr = Signal(2)
self.rxnotintable = Signal(2)
@ -124,6 +123,9 @@ class GTXE2_CHANNEL(Module):
}
rxcdr_cfg = cdr_config[start_speed]
rxdata = Signal(16)
rxcharisk = Signal(2)
self.specials += \
Instance("GTXE2_CHANNEL",
# Simulation-Only Attributes
@ -492,7 +494,7 @@ class GTXE2_CHANNEL(Module):
i_RXUSRCLK2=self.rxusrclk2,
# Receive Ports - FPGA RX interface Ports
i_RXDATA=self.rxdata,
i_RXDATA=rxdata,
# Receive Ports - Pattern Checker Ports
#o_RXPRBSERR=,
@ -629,8 +631,8 @@ class GTXE2_CHANNEL(Module):
i_RXSLIDE=0,
# Receive Ports - RX8B/10B Decoder Ports
o_RXCHARISCOMMA=self.rxchariscomma,
o_RXCHARISK=self.rxcharisk,
#o_RXCHARISCOMMA=,
o_RXCHARISK=rxcharisk,
# Receive Ports - Rx Channel Bonding Ports
i_RXCHBONDI=0,
@ -759,3 +761,22 @@ class GTXE2_CHANNEL(Module):
#o_TXQPISENN=,
#o_TXQPISENP=
)
# realign rxdata / rxcharisk
rxdata_r = Signal(dw)
rxcharisk_r = Signal(dw//8)
self.sync.sata_rx += [
rxdata_r.eq(rxdata),
rxcharisk_r.eq(rxcharisk)
]
cases = {}
cases[1<<0] = [
self.rxdata.eq(rx_data_r[0:dw]),
self.rxcharisk.eq(rx_charisk_r[0:dw//8])
]
for i in range(1, dw//8):
cases[1<<i] = [
self.rxdata.eq(Cat(self.gtx.rxdata[8*i:dw], rxdata_r[0:8*i])),
self.rxcharisk.eq(Cat(self.gtx.rxcharisk[i:dw//8], rxcharisk_r[0:i]))
]
self.comb += Case(rxcharisk_d, cases)