soc/jtag: run JTAGPHY in sys_jtag clock domain (to fix behavior after reset).

litex/soc/cores/jtag.py

@@ -130,7 +130,7 @@ class JTAGPHY(Module):
         # JTAG clock domain ------------------------------------------------------------------------
         self.clock_domains.cd_jtag = ClockDomain()
         self.comb += ClockSignal("jtag").eq(jtag.tck)
-        self.specials += AsyncResetSynchronizer(self.cd_jtag, ResetSignal("sys"))
+        self.specials += AsyncResetSynchronizer(self.cd_jtag, ResetSignal(clock_domain))
 
         # JTAG clock domain crossing ---------------------------------------------------------------
         if clock_domain != "jtag":

litex/soc/integration/soc.py

@@ -1130,7 +1130,9 @@ class LiteXSoC(SoC):
         # JTAG UART
         elif name in ["jtag_uart"]:
             from litex.soc.cores.jtag import JTAGPHY
-            self.submodules.uart_phy = JTAGPHY(device=self.platform.device)
+            self.clock_domains.cd_sys_jtag = ClockDomain()          # Run JTAG-UART in sys_jtag clock domain similar to
+            self.comb += self.cd_sys_jtag.clk.eq(ClockSignal("sys")) # sys clock domain but with rst disconnected.
+            self.submodules.uart_phy = JTAGPHY(device=self.platform.device, clock_domain="sys_jtag")
             self.submodules.uart = uart.UART(self.uart_phy,
                 tx_fifo_depth = fifo_depth,
                 rx_fifo_depth = fifo_depth)