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soc/jtag: run JTAGPHY in sys_jtag clock domain (to fix behavior after reset).

This commit is contained in:
Florent Kermarrec 2021-01-25 16:31:55 +01:00
parent 213644af70
commit 7799765471
2 changed files with 4 additions and 2 deletions
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2
litex/soc/cores/jtag.py
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@ -130,7 +130,7 @@ class JTAGPHY(Module):
# JTAG clock domain ------------------------------------------------------------------------ # JTAG clock domain ------------------------------------------------------------------------
self.clock_domains.cd_jtag = ClockDomain() self.clock_domains.cd_jtag = ClockDomain()
self.comb += ClockSignal("jtag").eq(jtag.tck) self.comb += ClockSignal("jtag").eq(jtag.tck)
self.specials += AsyncResetSynchronizer(self.cd_jtag, ResetSignal("sys")) self.specials += AsyncResetSynchronizer(self.cd_jtag, ResetSignal(clock_domain))
# JTAG clock domain crossing --------------------------------------------------------------- # JTAG clock domain crossing ---------------------------------------------------------------
if clock_domain != "jtag": if clock_domain != "jtag":

4
litex/soc/integration/soc.py
View File

@ -1130,7 +1130,9 @@ class LiteXSoC(SoC):
# JTAG UART # JTAG UART
elif name in ["jtag_uart"]: elif name in ["jtag_uart"]:
from litex.soc.cores.jtag import JTAGPHY from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=self.platform.device) self.clock_domains.cd_sys_jtag = ClockDomain() # Run JTAG-UART in sys_jtag clock domain similar to
self.comb += self.cd_sys_jtag.clk.eq(ClockSignal("sys")) # sys clock domain but with rst disconnected.
self.submodules.uart_phy = JTAGPHY(device=self.platform.device, clock_domain="sys_jtag")
self.submodules.uart = uart.UART(self.uart_phy, self.submodules.uart = uart.UART(self.uart_phy,
tx_fifo_depth = fifo_depth, tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth) rx_fifo_depth = fifo_depth)