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tools/litex_sim: Update Etherbone/Ethernet hybrid mode integration.

This commit is contained in:
Florent Kermarrec 2023-11-10 19:13:35 +01:00
parent 57782309a2
commit 77ca872b3b
1 changed files with 19 additions and 19 deletions
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36
litex/tools/litex_sim.py
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@ -235,27 +235,25 @@ class SimSoC(SoCCore):
# Ethernet and Etherbone ------------------------------------------------------------------- # Ethernet and Etherbone -------------------------------------------------------------------
if with_ethernet and with_etherbone: if with_ethernet and with_etherbone:
etherbone_ip_address = convert_ip(etherbone_ip_address) # Etherbone.
# Ethernet MAC self.add_etherbone(
self.ethmac = LiteEthMAC(phy=self.ethphy, dw=8, phy = self.ethphy,
ip_address = etherbone_ip_address,
mac_address = etherbone_mac_address,
data_width = 8,
interface = "hybrid", interface = "hybrid",
endianness = self.cpu.endianness, endianness = self.cpu.endianness
hw_mac = etherbone_mac_address) )
# SoftCPU # Software Interface.
ethmac_region_size = (self.ethmac.rx_slots.constant + self.ethmac.tx_slots.constant)*self.ethmac.slot_size.constant self.ethmac = ethmac = self.get_module("ethcore_etherbone").mac
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region) self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
# Add IRQs (if enabled).
if self.irq.enabled: if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True) self.irq.add("ethmac", use_loc_if_exists=True)
# HW ethernet
self.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8)
self.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8)
self.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8)
self.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8)
# Etherbone
self.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.bus.add_master(name="etherbone", master=self.etherbone.wishbone.bus)
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------
elif with_ethernet: elif with_ethernet:
@ -264,11 +262,13 @@ class SimSoC(SoCCore):
phy = self.ethphy, phy = self.ethphy,
dw = 64 if ethernet_phy_model == "xgmii" else 32, dw = 64 if ethernet_phy_model == "xgmii" else 32,
interface = "wishbone", interface = "wishbone",
endianness = self.cpu.endianness) endianness = self.cpu.endianness
# Compute Regions size and add it to the SoC. )
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False) ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region) self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
# Add IRQs (if enabled).
if self.irq.enabled: if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True) self.irq.add("ethmac", use_loc_if_exists=True)