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core/spi: make cs_n optional (sometimes managed externally)

This commit is contained in:
Florent Kermarrec 2019-07-05 19:18:52 +02:00
parent e726ad80ac
commit 77e7f9b3c1
1 changed files with 5 additions and 3 deletions
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8
litex/soc/cores/spi.py
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@ -30,7 +30,8 @@ class SPIMaster(Module, AutoCSR):
self._status = CSRStatus(1) self._status = CSRStatus(1)
self._mosi = CSRStorage(data_width) self._mosi = CSRStorage(data_width)
self._miso = CSRStatus(data_width) self._miso = CSRStatus(data_width)
self._cs = CSRStorage(len(pads.cs_n), reset=1) if hasattr(pads, "cs_n"):
self._cs = CSRStorage(len(pads.cs_n), reset=1)
self.irq = Signal() self.irq = Signal()
@ -101,8 +102,9 @@ class SPIMaster(Module, AutoCSR):
) )
# Chip Select generation ------------------------------------------------------------------- # Chip Select generation -------------------------------------------------------------------
for i in range(len(pads.cs_n)): if hasattr(pads, "cs_n"):
self.comb += pads.cs_n[i].eq(~self._cs.storage[i] | ~cs) for i in range(len(pads.cs_n)):
self.comb += pads.cs_n[i].eq(~self._cs.storage[i] | ~cs)
# Master Out Slave In (MOSI) generation (generated on spi_clk falling edge) --------------- # Master Out Slave In (MOSI) generation (generated on spi_clk falling edge) ---------------
mosi_data = Signal(data_width) mosi_data = Signal(data_width)