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tools/litex_sim/generate_gtkw_savefile: Check main_ram presence.

This commit is contained in:
Florent Kermarrec 2021-09-28 10:02:17 +02:00
parent de738e153d
commit 782744bae3
1 changed files with 3 additions and 2 deletions
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5
litex/tools/litex_sim.py
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@ -314,9 +314,10 @@ def generate_gtkw_savefile(builder, vns, trace_fst):
with gtkw.GTKWSave(vns, savefile=savefile, dumpfile=dumpfile) as save: with gtkw.GTKWSave(vns, savefile=savefile, dumpfile=dumpfile) as save:
save.clocks() save.clocks()
save.fsm_states(soc) save.fsm_states(soc)
save.add(soc.bus.slaves["main_ram"], mappers=[gtkw.wishbone_sorter(), gtkw.wishbone_colorer()]) if "main_ram" in soc.bus.slaves.keys():
save.add(soc.bus.slaves["main_ram"], mappers=[gtkw.wishbone_sorter(), gtkw.wishbone_colorer()])
if hasattr(soc, 'sdrphy'): if hasattr(soc, "sdrphy"):
# all dfi signals # all dfi signals
save.add(soc.sdrphy.dfi, mappers=[gtkw.dfi_sorter(), gtkw.dfi_in_phase_colorer()]) save.add(soc.sdrphy.dfi, mappers=[gtkw.dfi_sorter(), gtkw.dfi_in_phase_colorer()])