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build.py: LOC clock generator components to limit breakage of the ISE shitware

This commit is contained in:
Sebastien Bourdeauducq 2013-05-05 23:07:15 +02:00
parent 11cbdf0d4f
commit 784e96bb87
1 changed files with 2 additions and 0 deletions
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build.py
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@ -18,6 +18,8 @@ TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
""", clk50=platform.lookup_request("clk50")) """, clk50=platform.lookup_request("clk50"))
platform.add_platform_command(""" platform.add_platform_command("""
INST "m1crg/pll" LOC="PLL_ADV_X0Y1";
INST "m1crg/vga_clock_gen" LOC="DCM_X0Y6";
INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2"; INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3"; INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";