simplify RLE
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parent
87f29a307a
commit
788652c6f8
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@ -1,4 +1,5 @@
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from litescope.common import *
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from migen.flow.plumbing import Buffer
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class LiteScopeSubSamplerUnit(Module):
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def __init__(self, dw):
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@ -33,38 +34,37 @@ class LiteScopeRunLengthEncoderUnit(Module):
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self.enable = Signal()
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###
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sink_d = Sink(data_layout(dw))
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self.sync += If(sink.stb, sink_d.eq(sink))
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self.submodules.buf = buf = Buffer(sink.description)
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self.comb += Record.connect(sink, buf.d)
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cnt = Signal(max=length)
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cnt_inc = Signal()
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cnt_reset = Signal()
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cnt_max = Signal()
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self.sync += \
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If(cnt_reset,
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cnt.eq(1),
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).Elif(cnt_inc,
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cnt.eq(cnt+1)
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)
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self.comb += cnt_max.eq(cnt == length)
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self.submodules.counter = counter = Counter(max=length)
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counter_done = Signal()
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self.comb += counter_done.eq(counter.value == length-1)
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change = Signal()
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self.comb += change.eq(sink.stb & (sink.dat != sink_d.dat))
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self.comb += change.eq(
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(sink.stb & buf.q.stb) &
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(sink.data != buf.q.data)
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)
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fsm = FSM(reset_state="BYPASS")
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self.submodules += fsm
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self.submodules.fsm = fsm = FSM(reset_state="BYPASS")
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fsm.act("BYPASS",
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Record.connect(sink_d, source),
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cnt_reset.eq(1),
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If(self.enable & ~change & sink.stb, NextState("COUNT"))
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Record.connect(buf.q, source),
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counter.reset.eq(1),
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If(sink.stb & ~change,
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If(self.enable,
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NextState("COUNT")
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)
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)
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)
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fsm.act("COUNT",
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cnt_inc.eq(sink.stb),
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If(change | cnt_max | ~self.enable,
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counter.ce.eq(sink.stb),
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If(~self.enable,
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NextState("BYPASS")
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).Elif(change | counter_done,
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source.stb.eq(1),
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source.dat[dw-1].eq(1), # Set RLE bit
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source.dat[:flen(cnt)].eq(cnt),
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source.data[:flen(counter.value)].eq(counter.value),
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source.data[-1].eq(1), # Set RLE bit
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NextState("BYPASS")
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)
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)
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@ -74,7 +74,7 @@ class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR):
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LiteScopeRunLengthEncoderUnit.__init__(self, dw, length)
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self._enable = CSRStorage()
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###
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self.comb += self.enable.eq(self_enable.storage)
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self.comb += self.enable.eq(self._enable.storage)
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class LiteScopeRecorderUnit(Module):
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def __init__(self, dw, depth):
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@ -56,11 +56,10 @@ class LiteScopeLA(Module, AutoCSR):
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# connect recorder
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self.comb += Record.connect(self.trigger.source, self.recorder.trigger_sink)
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if self.with_rle:
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rle = LiteScopeRunLengthEncoder(self.dw)
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self.submodules += rle
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self.submodules.rle = LiteScopeRunLengthEncoder(self.dw)
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self.comb += [
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Record.connect(sink, rle.sink),
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Record.connect(rle.source, self.recorder.data_sink)
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Record.connect(sink, self.rle.sink),
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Record.connect(self.rle.source, self.recorder.data_sink)
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]
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else:
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self.submodules.delay_buffer = Buffer(self.sink.description)
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@ -5,17 +5,16 @@ from litescope.host.dump import *
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from litescope.host.driver.truthtable import *
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class LiteScopeLADriver():
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def __init__(self, regs, name, config_csv=None, use_rle=False, debug=False):
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def __init__(self, regs, name, config_csv=None, debug=False):
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self.regs = regs
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self.name = name
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self.use_rle = use_rle
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self.debug = debug
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if config_csv is None:
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self.config_csv = name + ".csv"
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self.get_config()
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self.get_layout()
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self.build()
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self.dat = Dat(self.dw)
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self.data = Dat(self.dw)
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def get_config(self):
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csv_reader = csv.reader(open(self.config_csv), delimiter=',', quotechar='#')
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@ -92,8 +91,6 @@ class LiteScopeLADriver():
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def run(self, offset, length):
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if self.debug:
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print("running")
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if self.with_rle:
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self.config_rle(self.use_rle)
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self.recorder_offset.write(offset)
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self.recorder_length.write(length)
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self.recorder_trigger.write(1)
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@ -102,12 +99,12 @@ class LiteScopeLADriver():
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if self.debug:
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print("uploading")
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while self.recorder_source_stb.read():
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self.dat.append(self.recorder_source_data.read())
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self.data.append(self.recorder_source_data.read())
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self.recorder_source_ack.write(1)
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if self.with_rle:
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if self.use_rle:
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self.dat = self.dat.decode_rle()
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return self.dat
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if self.rle_enable.read():
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self.data = self.data.decode_rle()
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return self.data
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def save(self, filename):
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if self.debug:
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@ -127,5 +124,5 @@ class LiteScopeLADriver():
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dump = SigrokDump()
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else:
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raise NotImplementedError
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dump.add_from_layout(self.layout, self.dat)
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dump.add_from_layout(self.layout, self.data)
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dump.write(filename)
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@ -12,6 +12,7 @@ class SigrokDump(Dump):
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Dump.__init__(self)
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if init_dump:
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self.vars = init_dump.vars
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self.samplerate = samplerate
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def write_version(self):
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f = open("version", "w")
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@ -87,17 +87,21 @@ class LiteScopeSoC(GenSoC, AutoCSR):
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self.leds = Cat(*[platform.request("user_led", i) for i in range(8)])
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self.comb += self.leds.eq(self.io.o)
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cnt0 = Signal(8)
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cnt1 = Signal(8)
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self.sync += [
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cnt0.eq(cnt0+1),
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cnt1.eq(cnt1+2)
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self.submodules.counter0 = counter0 = Counter(bits_sign=8)
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self.submodules.counter1 = counter1 = Counter(bits_sign=8)
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self.comb += [
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counter0.ce.eq(1),
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If(counter0.value == 16,
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counter0.reset.eq(1),
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counter1.ce.eq(1)
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)
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]
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self.debug = (
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cnt0,
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cnt1
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counter1.value,
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Signal()
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)
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self.submodules.la = LiteScopeLA(self.debug, 512, with_subsampler=True)
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self.submodules.la = LiteScopeLA(self.debug, 512, with_rle=True, with_subsampler=True)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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def do_exit(self, vns):
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@ -5,11 +5,13 @@ wb.open()
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###
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la = LiteScopeLADriver(wb.regs, "la", debug=True)
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cond = {"cnt0" : 128} # trigger on cnt0 = 128
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#cond = {"cnt0" : 128} # trigger on cnt0 = 128
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cond = {} # trigger on cnt0 = 128
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la.configure_term(port=0, cond=cond)
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la.configure_sum("term")
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la.configure_subsampler(1)
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la.configure_qualifier(1)
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#la.configure_qualifier(1)
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la.configure_rle(1)
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la.run(offset=128, length=256)
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while not la.done():
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