simplify RLE

This commit is contained in:
Florent Kermarrec 2015-02-18 23:35:41 +01:00
parent 87f29a307a
commit 788652c6f8
6 changed files with 52 additions and 49 deletions

View File

@ -1,4 +1,5 @@
from litescope.common import *
from migen.flow.plumbing import Buffer
class LiteScopeSubSamplerUnit(Module):
def __init__(self, dw):
@ -33,38 +34,37 @@ class LiteScopeRunLengthEncoderUnit(Module):
self.enable = Signal()
###
sink_d = Sink(data_layout(dw))
self.sync += If(sink.stb, sink_d.eq(sink))
self.submodules.buf = buf = Buffer(sink.description)
self.comb += Record.connect(sink, buf.d)
cnt = Signal(max=length)
cnt_inc = Signal()
cnt_reset = Signal()
cnt_max = Signal()
self.sync += \
If(cnt_reset,
cnt.eq(1),
).Elif(cnt_inc,
cnt.eq(cnt+1)
)
self.comb += cnt_max.eq(cnt == length)
self.submodules.counter = counter = Counter(max=length)
counter_done = Signal()
self.comb += counter_done.eq(counter.value == length-1)
change = Signal()
self.comb += change.eq(sink.stb & (sink.dat != sink_d.dat))
self.comb += change.eq(
(sink.stb & buf.q.stb) &
(sink.data != buf.q.data)
)
fsm = FSM(reset_state="BYPASS")
self.submodules += fsm
self.submodules.fsm = fsm = FSM(reset_state="BYPASS")
fsm.act("BYPASS",
Record.connect(sink_d, source),
cnt_reset.eq(1),
If(self.enable & ~change & sink.stb, NextState("COUNT"))
Record.connect(buf.q, source),
counter.reset.eq(1),
If(sink.stb & ~change,
If(self.enable,
NextState("COUNT")
)
)
)
fsm.act("COUNT",
cnt_inc.eq(sink.stb),
If(change | cnt_max | ~self.enable,
counter.ce.eq(sink.stb),
If(~self.enable,
NextState("BYPASS")
).Elif(change | counter_done,
source.stb.eq(1),
source.dat[dw-1].eq(1), # Set RLE bit
source.dat[:flen(cnt)].eq(cnt),
source.data[:flen(counter.value)].eq(counter.value),
source.data[-1].eq(1), # Set RLE bit
NextState("BYPASS")
)
)
@ -74,7 +74,7 @@ class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR):
LiteScopeRunLengthEncoderUnit.__init__(self, dw, length)
self._enable = CSRStorage()
###
self.comb += self.enable.eq(self_enable.storage)
self.comb += self.enable.eq(self._enable.storage)
class LiteScopeRecorderUnit(Module):
def __init__(self, dw, depth):

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@ -56,11 +56,10 @@ class LiteScopeLA(Module, AutoCSR):
# connect recorder
self.comb += Record.connect(self.trigger.source, self.recorder.trigger_sink)
if self.with_rle:
rle = LiteScopeRunLengthEncoder(self.dw)
self.submodules += rle
self.submodules.rle = LiteScopeRunLengthEncoder(self.dw)
self.comb += [
Record.connect(sink, rle.sink),
Record.connect(rle.source, self.recorder.data_sink)
Record.connect(sink, self.rle.sink),
Record.connect(self.rle.source, self.recorder.data_sink)
]
else:
self.submodules.delay_buffer = Buffer(self.sink.description)

View File

@ -5,17 +5,16 @@ from litescope.host.dump import *
from litescope.host.driver.truthtable import *
class LiteScopeLADriver():
def __init__(self, regs, name, config_csv=None, use_rle=False, debug=False):
def __init__(self, regs, name, config_csv=None, debug=False):
self.regs = regs
self.name = name
self.use_rle = use_rle
self.debug = debug
if config_csv is None:
self.config_csv = name + ".csv"
self.get_config()
self.get_layout()
self.build()
self.dat = Dat(self.dw)
self.data = Dat(self.dw)
def get_config(self):
csv_reader = csv.reader(open(self.config_csv), delimiter=',', quotechar='#')
@ -92,8 +91,6 @@ class LiteScopeLADriver():
def run(self, offset, length):
if self.debug:
print("running")
if self.with_rle:
self.config_rle(self.use_rle)
self.recorder_offset.write(offset)
self.recorder_length.write(length)
self.recorder_trigger.write(1)
@ -102,12 +99,12 @@ class LiteScopeLADriver():
if self.debug:
print("uploading")
while self.recorder_source_stb.read():
self.dat.append(self.recorder_source_data.read())
self.data.append(self.recorder_source_data.read())
self.recorder_source_ack.write(1)
if self.with_rle:
if self.use_rle:
self.dat = self.dat.decode_rle()
return self.dat
if self.rle_enable.read():
self.data = self.data.decode_rle()
return self.data
def save(self, filename):
if self.debug:
@ -127,5 +124,5 @@ class LiteScopeLADriver():
dump = SigrokDump()
else:
raise NotImplementedError
dump.add_from_layout(self.layout, self.dat)
dump.add_from_layout(self.layout, self.data)
dump.write(filename)

View File

@ -12,6 +12,7 @@ class SigrokDump(Dump):
Dump.__init__(self)
if init_dump:
self.vars = init_dump.vars
self.samplerate = samplerate
def write_version(self):
f = open("version", "w")

View File

@ -87,17 +87,21 @@ class LiteScopeSoC(GenSoC, AutoCSR):
self.leds = Cat(*[platform.request("user_led", i) for i in range(8)])
self.comb += self.leds.eq(self.io.o)
cnt0 = Signal(8)
cnt1 = Signal(8)
self.sync += [
cnt0.eq(cnt0+1),
cnt1.eq(cnt1+2)
]
self.debug = (
cnt0,
cnt1
self.submodules.counter0 = counter0 = Counter(bits_sign=8)
self.submodules.counter1 = counter1 = Counter(bits_sign=8)
self.comb += [
counter0.ce.eq(1),
If(counter0.value == 16,
counter0.reset.eq(1),
counter1.ce.eq(1)
)
self.submodules.la = LiteScopeLA(self.debug, 512, with_subsampler=True)
]
self.debug = (
counter1.value,
Signal()
)
self.submodules.la = LiteScopeLA(self.debug, 512, with_rle=True, with_subsampler=True)
self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
def do_exit(self, vns):

View File

@ -5,11 +5,13 @@ wb.open()
###
la = LiteScopeLADriver(wb.regs, "la", debug=True)
cond = {"cnt0" : 128} # trigger on cnt0 = 128
#cond = {"cnt0" : 128} # trigger on cnt0 = 128
cond = {} # trigger on cnt0 = 128
la.configure_term(port=0, cond=cond)
la.configure_sum("term")
la.configure_subsampler(1)
la.configure_qualifier(1)
#la.configure_qualifier(1)
la.configure_rle(1)
la.run(offset=128, length=256)
while not la.done():