arp: add cached_valid signal, UDP tx works on hardware

This commit is contained in:
Florent Kermarrec 2015-02-05 20:10:09 +01:00
parent 1ae204b7a1
commit 78a85e3bbc
4 changed files with 27 additions and 15 deletions

View File

@ -142,7 +142,7 @@ class LiteEthARPTable(Module):
self.request = request = Sink(arp_table_request_layout)
self.response = response = Source(arp_table_response_layout)
###
request_timeout = Timeout(512) # XXX fix me 100ms?
request_timeout = Timeout(166000000//10) # XXX use clk_freq
request_pending = FlipFlop()
request_ip_address = FlipFlop(32, reset=0xffffffff) # XXX add cached_valid?
self.submodules += request_timeout, request_pending, request_ip_address
@ -155,6 +155,7 @@ class LiteEthARPTable(Module):
# Note: Store only one ip/mac couple, replace this with
# a real ARP table
update = Signal()
cached_valid = Signal()
cached_ip_address = Signal(32)
cached_mac_address = Signal(48)
@ -185,6 +186,7 @@ class LiteEthARPTable(Module):
)
self.sync += [
If(update,
cached_valid.eq(1),
cached_ip_address.eq(sink.ip_address),
cached_mac_address.eq(sink.mac_address)
)
@ -192,6 +194,7 @@ class LiteEthARPTable(Module):
found = Signal()
fsm.act("CHECK_TABLE",
# XXX: add a live time for cached_mac_address
If(cached_valid,
If(request_ip_address.q == cached_ip_address,
request_ip_address.reset.eq(1),
NextState("PRESENT_RESPONSE"),
@ -199,14 +202,18 @@ class LiteEthARPTable(Module):
request.ack.eq(request.stb),
NextState("PRESENT_RESPONSE"),
).Else(
request_ip_address.ce.eq(1),
request_ip_address.ce.eq(request.stb),
NextState("SEND_REQUEST")
)
).Else(
request_ip_address.ce.eq(request.stb),
NextState("SEND_REQUEST")
)
)
fsm.act("SEND_REQUEST",
source.stb.eq(1),
source.request.eq(1),
source.ip_address.eq(request.ip_address),
source.ip_address.eq(request_ip_address.q),
If(source.ack,
request_timeout.reset.eq(1),
request_pending.ce.eq(1),

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@ -50,7 +50,7 @@ class LiteEthIPTX(Module):
packetizer.sink.sop.eq(self.sink.sop),
packetizer.sink.eop.eq(self.sink.eop),
self.sink.ack.eq(packetizer.sink.ack),
packetizer.sink.target_ip.eq(ip_address),
packetizer.sink.target_ip.eq(self.sink.ip_address),
packetizer.sink.protocol.eq(self.sink.protocol),
packetizer.sink.total_length.eq(self.sink.length + (0x5*4)),
packetizer.sink.version.eq(0x4), # ipv4

View File

@ -50,7 +50,7 @@ class _CRG(Module):
p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
),
Instance("BUFG", i_I=ClockSignal("eth_tx"), o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
]
@ -170,7 +170,7 @@ class UDPIPSoC(GenSoC, AutoCSR):
}
csr_map.update(GenSoC.csr_map)
def __init__(self, platform):
clk_freq = 125*1000000
clk_freq = 166*1000000
GenSoC.__init__(self, platform, clk_freq)
self.submodules.crg = _CRG(platform)
@ -199,6 +199,7 @@ class UDPIPSoCDevel(UDPIPSoC, AutoCSR):
self.udpip_core_ip_tx_fsm_state = Signal(4)
self.udpip_core_arp_rx_fsm_state = Signal(4)
self.udpip_core_arp_tx_fsm_state = Signal(4)
self.udpip_core_arp_table_fsm_state = Signal(4)
debug = (
self.udpip_core.mac.core.sink.stb,
@ -230,7 +231,9 @@ class UDPIPSoCDevel(UDPIPSoC, AutoCSR):
self.udpip_core_ip_rx_fsm_state,
self.udpip_core_ip_tx_fsm_state,
self.udpip_core_arp_rx_fsm_state,
self.udpip_core_arp_tx_fsm_state
self.udpip_core_arp_tx_fsm_state,
self.udpip_core_arp_table_fsm_state,
)
self.submodules.la = LiteScopeLA(debug, 2048)
@ -245,7 +248,8 @@ class UDPIPSoCDevel(UDPIPSoC, AutoCSR):
self.udpip_core_ip_rx_fsm_state.eq(self.udpip_core.ip.rx.fsm.state),
self.udpip_core_ip_tx_fsm_state.eq(self.udpip_core.ip.tx.fsm.state),
self.udpip_core_arp_rx_fsm_state.eq(self.udpip_core.arp.rx.fsm.state),
self.udpip_core_arp_tx_fsm_state.eq(self.udpip_core.arp.tx.fsm.state)
self.udpip_core_arp_tx_fsm_state.eq(self.udpip_core.arp.tx.fsm.state),
self.udpip_core_arp_table_fsm_state.eq(self.udpip_core.arp.table.fsm.state)
]
def exit(self, platform):

View File

@ -31,7 +31,8 @@ la.configure_sum("term")
# Run Logic Analyzer
la.run(offset=64, length=1024)
regs.bist_generator_start.write(1)
for i in range(64):
regs.bist_generator_start.write(1)
while not la.done():
pass