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cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word.

This commit is contained in:
Florent Kermarrec 2020-05-25 10:46:53 +02:00
parent 370e46529d
commit 78a9579e09
1 changed files with 3 additions and 6 deletions
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9
litex/soc/cores/uart.py
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@ -99,7 +99,8 @@ class RS232PHYTX(Module):
If(self.sink.valid & ~tx_busy & ~self.sink.ready, If(self.sink.valid & ~tx_busy & ~self.sink.ready,
tx_reg.eq(self.sink.data), tx_reg.eq(self.sink.data),
tx_bitcount.eq(0), tx_bitcount.eq(0),
tx_busy.eq(1) tx_busy.eq(1),
pads.tx.eq(0)
).Elif(uart_clk_txen & tx_busy, ).Elif(uart_clk_txen & tx_busy,
tx_bitcount.eq(tx_bitcount + 1), tx_bitcount.eq(tx_bitcount + 1),
If(tx_bitcount == 8, If(tx_bitcount == 8,
@ -112,17 +113,13 @@ class RS232PHYTX(Module):
pads.tx.eq(tx_reg[0]), pads.tx.eq(tx_reg[0]),
tx_reg.eq(Cat(tx_reg[1:], 0)) tx_reg.eq(Cat(tx_reg[1:], 0))
) )
).Elif(tx_busy,
If(tx_bitcount == 0,
pads.tx.eq(0)
)
) )
] ]
self.sync += [ self.sync += [
If(tx_busy, If(tx_busy,
Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word) Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word)
).Else( ).Else(
Cat(phase_accumulator_tx, uart_clk_txen).eq(0) Cat(phase_accumulator_tx, uart_clk_txen).eq(tuning_word)
) )
] ]