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cpu/vexriscv: Simplify CFU integration, use Cfu.v as default CFU when not specified and rename argument to --cpu-cfu.

This commit is contained in:
Florent Kermarrec 2021-05-17 10:01:41 +02:00
parent 87bb10f43b
commit 78bdde0424
3 changed files with 14 additions and 12 deletions
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2
CHANGES
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@ -7,7 +7,7 @@
[> Added Features
-----------------
-
- cpu/vexriscv: Add CFU support.
[> API changes/Deprecation
--------------------------

11
litex/soc/cores/cpu/vexriscv/core.py
View File

@ -101,7 +101,7 @@ class VexRiscv(CPU, AutoCSR):
gcc_triple = CPU_GCC_TRIPLE_RISCV32
linker_output_format = "elf32-littleriscv"
nop = "nop"
io_regions = {0x80000000: 0x80000000} # origin, length
io_regions = {0x80000000: 0x80000000} # Origin, Length
# Memory Mapping.
@property
@ -121,7 +121,7 @@ class VexRiscv(CPU, AutoCSR):
flags += " -D__vexriscv__"
return flags
def __init__(self, platform, variant="standard", with_timer=False):
def __init__(self, platform, variant="standard", with_timer=False, cfu=None):
self.platform = platform
self.variant = variant
self.human_name = CPU_VARIANTS.get(variant, "VexRiscv")
@ -174,6 +174,9 @@ class VexRiscv(CPU, AutoCSR):
if "debug" in variant:
self.add_debug()
if "cfu" in variant:
self.add_cfu(cfu_filename="Cfu.v" if cfu is None else cfu)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
@ -268,6 +271,10 @@ class VexRiscv(CPU, AutoCSR):
)
def add_cfu(self, cfu_filename):
# Check CFU presence.
if not os.path.exists(cfu_filename):
raise OSError(f"Unable to find VexRiscv CFU plugin {cfu_filename}.")
# CFU Layout.
cfu_bus_layout = [
("cmd", [

13
litex/soc/integration/soc_core.py
View File

@ -71,6 +71,7 @@ class SoCCore(LiteXSoC):
cpu_reset_address = None,
cpu_variant = None,
cpu_cls = None,
cpu_cfu = None,
# CFU parameters
cfu_filename = None,
@ -186,8 +187,9 @@ class SoCCore(LiteXSoC):
self.add_cpu(
name = str(cpu_type),
variant = "standard" if cpu_variant is None else cpu_variant,
reset_address = None if integrated_rom_size else cpu_reset_address,
cls = cpu_cls,
reset_address = None if integrated_rom_size else cpu_reset_address)
cfu = cpu_cfu)
# Add User's interrupts
if self.irq.enabled:
@ -220,11 +222,6 @@ class SoCCore(LiteXSoC):
if timer_uptime:
self.timer0.add_uptime()
# Add CFU
if cfu_filename:
assert(cpu_type == "vexriscv")
self.cpu.add_cfu(cfu_filename=cfu_filename)
# Methods --------------------------------------------------------------------------------------
def add_interrupt(self, interrupt_name, interrupt_id=None, use_loc_if_exists=False):
@ -300,6 +297,7 @@ def soc_core_args(parser):
parser.add_argument("--cpu-type", default=None, help="Select CPU: {}, (default=vexriscv).".format(", ".join(iter(cpu.CPUS.keys()))))
parser.add_argument("--cpu-variant", default=None, help="CPU variant (default=standard).")
parser.add_argument("--cpu-reset-address", default=None, type=auto_int, help="CPU reset address (default=None : Boot from Integrated ROM).")
parser.add_argument("--cpu-cfu", default=None, help="Optional CPU CFU file/instance to add to the CPU.")
# Controller parameters
parser.add_argument("--no-ctrl", action="store_true", help="Disable Controller (default=False).")
@ -337,9 +335,6 @@ def soc_core_args(parser):
# L2 Cache
parser.add_argument("--l2-size", default=8192, type=auto_int, help="L2 cache size (default=8192).")
# CFU
parser.add_argument("--cfu-filename", default=None, help="CFU verilog filename.")
def soc_core_argdict(args):
r = dict()
for a in inspect.getargspec(SoCCore.__init__).args: