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soc/cores: rename frequency_meter to freqmeter and uniformize with others cores

This commit is contained in:
Florent Kermarrec 2019-09-29 16:08:39 +02:00
parent 7575ecc6ad
commit 78cecbe36b
1 changed files with 13 additions and 12 deletions
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25
litex/soc/cores/frequency_meter.py → litex/soc/cores/freqmeter.py
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@ -7,8 +7,9 @@ from migen.genlib.cdc import GrayDecoder
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
# Sampler ------------------------------------------------------------------------------------------
class Sampler(Module): class _Sampler(Module):
def __init__(self, width): def __init__(self, width):
self.latch = Signal() self.latch = Signal()
self.i = Signal(width) self.i = Signal(width)
@ -16,15 +17,14 @@ class Sampler(Module):
# # # # # #
inc = Signal(width) inc = Signal(width)
counter = Signal(32) counter = Signal(32)
# use wrapping property of unsigned arithmeric to reset the counter # Use wrapping property of unsigned arithmeric to reset the counter at each cycle. Doing
# each cycle (reseting fmeter clock domain is unreliable) # it in fmeter clock domain would not be reliable.
i_d = Signal(width) i_d = Signal(width)
self.sync += i_d.eq(self.i) self.sync += i_d.eq(self.i)
self.comb += inc.eq(self.i - i_d) self.comb += inc.eq(self.i - i_d)
self.sync += \ self.sync += \
If(self.latch, If(self.latch,
counter.eq(0), counter.eq(0),
@ -33,10 +33,11 @@ class Sampler(Module):
counter.eq(counter + inc) counter.eq(counter + inc)
) )
# Freq Meter ---------------------------------------------------------------------------------------
class FrequencyMeter(Module, AutoCSR): class FreqMeter(Module, AutoCSR):
def __init__(self, period, width=6, clk=None): def __init__(self, period, width=6, clk=None):
self.clk = Signal() if clk is None else clk self.clk = Signal() if clk is None else clk
self.value = CSRStatus(32) self.value = CSRStatus(32)
# # # # # #
@ -44,8 +45,8 @@ class FrequencyMeter(Module, AutoCSR):
self.clock_domains.cd_fmeter = ClockDomain(reset_less=True) self.clock_domains.cd_fmeter = ClockDomain(reset_less=True)
self.comb += self.cd_fmeter.clk.eq(self.clk) self.comb += self.cd_fmeter.clk.eq(self.clk)
# period generation # Period generation
period_done = Signal() period_done = Signal()
period_counter = Signal(32) period_counter = Signal(32)
self.comb += period_done.eq(period_counter == period) self.comb += period_done.eq(period_counter == period)
self.sync += \ self.sync += \
@ -55,10 +56,10 @@ class FrequencyMeter(Module, AutoCSR):
period_counter.eq(period_counter + 1) period_counter.eq(period_counter + 1)
) )
# frequency measurement # Frequency measurement
event_counter = ClockDomainsRenamer("fmeter")(GrayCounter(width)) event_counter = ClockDomainsRenamer("fmeter")(GrayCounter(width))
gray_decoder = GrayDecoder(width) gray_decoder = GrayDecoder(width)
sampler = Sampler(width) sampler = _Sampler(width)
self.submodules += event_counter, gray_decoder, sampler self.submodules += event_counter, gray_decoder, sampler
self.specials += MultiReg(event_counter.q, gray_decoder.i) self.specials += MultiReg(event_counter.q, gray_decoder.i)