cores/jtag: Make primitive selection more flexible (and simplify new devices support).
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@ -235,13 +235,42 @@ class AlteraJTAG(Module):
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]
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]
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self.sync.jtag_inv += tdouser.eq(tdo)
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self.sync.jtag_inv += tdouser.eq(tdo)
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class MAX10JTAG(AlteraJTAG):
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@staticmethod
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def __init__(self, *args, **kwargs):
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def get_primitive(device):
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AlteraJTAG.__init__(self, "fiftyfivenm_jtag", *args, **kwargs)
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# TODO: Add support for all devices.
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prim_dict = {
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class Cyclone10LPJTAG(AlteraJTAG):
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# Primitive Name Ðevice (startswith)
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def __init__(self, *args, **kwargs):
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"arriaii_jtag" : [],
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AlteraJTAG.__init__(self, "cyclone10lp_jtag", *args, **kwargs)
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"arriaiigz_jtag" : [],
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"arriav_jtag" : [],
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"arriavgz_jtag" : [],
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"cyclone_jtag" : [],
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"cyclone10lp_jtag" : ["10cl"],
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"cycloneii_jtag" : [],
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"cycloneiii_jtag" : [],
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"cycloneiiils_jtag" : [],
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"cycloneiv_jtag" : [],
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"cycloneive_jtag" : ["ep4c"],
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"cyclonev_jtag" : ["5c"],
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"fiftyfivenm_jtag" : ["10m"],
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"maxii_jtag" : [],
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"maxv_jtag" : [],
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"stratix_jtag" : [],
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"stratixgx_jtag" : [],
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"stratixii_jtag" : [],
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"stratixiigx_jtag" : [],
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"stratixiii_jtag" : [],
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"stratixiv_jtag" : [],
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"stratixv_jtag" : [],
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"twentynm_jtagblock" : [],
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"twentynm_jtag" : [],
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"twentynm_hps_interface_jtag" : [],
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}
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for prim, prim_devs in prim_dict.items():
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for prim_dev in prim_devs:
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if device.lower().startswith(prim_dev):
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return prim
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return None
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# Xilinx JTAG --------------------------------------------------------------------------------------
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# Xilinx JTAG --------------------------------------------------------------------------------------
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@ -273,19 +302,19 @@ class XilinxJTAG(Module):
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i_TDO = self.tdo,
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i_TDO = self.tdo,
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)
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)
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class S6JTAG(XilinxJTAG):
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@staticmethod
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def __init__(self, *args, **kwargs):
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def get_primitive(device):
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XilinxJTAG.__init__(self, primitive="BSCAN_SPARTAN6", *args, **kwargs)
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# TODO: Add support for all devices.
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prim_dict = {
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# Primitive Name Ðevice (startswith)
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class S7JTAG(XilinxJTAG):
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"BSCAN_SPARTAN6" : ["xc6"],
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def __init__(self, *args, **kwargs):
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"BSCANE2" : ["xc7", "xcku", "xcvu"],
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XilinxJTAG.__init__(self, primitive="BSCANE2", *args, **kwargs)
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}
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for prim, prim_devs in prim_dict.items():
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for prim_dev in prim_devs:
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class USJTAG(XilinxJTAG):
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if device.lower().startswith(prim_dev):
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def __init__(self, *args, **kwargs):
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return prim
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XilinxJTAG.__init__(self, primitive="BSCANE2", *args, **kwargs)
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return None
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# ECP5 JTAG ----------------------------------------------------------------------------------------
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# ECP5 JTAG ----------------------------------------------------------------------------------------
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@ -371,24 +400,18 @@ class JTAGPHY(Module):
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# JTAG TAP ---------------------------------------------------------------------------------
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# JTAG TAP ---------------------------------------------------------------------------------
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if jtag is None:
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if jtag is None:
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# Xilinx.
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# Xilinx.
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if device[:3] == "xc6":
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if XilinxJTAG.get_primitive(device) is not None:
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jtag = S6JTAG(chain=chain)
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jtag = XilinxJTAG(primitive=XilinxJTAG.get_primitive(device))
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elif device[:3] == "xc7":
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jtag = S7JTAG(chain=chain)
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elif device[:4] in ["xcku", "xcvu"]:
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jtag = USJTAG(chain=chain)
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# Lattice.
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# Lattice.
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elif device[:5] == "LFE5U":
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elif device[:5] == "LFE5U":
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jtag = ECP5JTAG()
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jtag = ECP5JTAG()
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# Altera/Intel.
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# Altera/Intel.
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elif device[:3].lower() in ["10m"]:
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elif AlteraJTAG.get_primitive(device) is not None:
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platform.add_reserved_jtag_decls()
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platform.add_reserved_jtag_decls()
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jtag = MAX10JTAG(pads=platform.get_reserved_jtag_pads())
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jtag = AlteraJTAG(
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elif device[:4].lower() in ["10cl"]:
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primitive = AlteraJTAG.get_primitive(device),
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platform.add_reserved_jtag_decls()
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pads = platform.get_reserved_jtag_pads()
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jtag = Cyclone10LPJTAG(pads=platform.get_reserved_jtag_pads())
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)
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else:
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else:
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print(device)
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print(device)
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raise NotImplementedError
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raise NotImplementedError
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