bus/asmi: port sharing support
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f202946717
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@ -1,6 +1,7 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module, FinalizeError
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from migen.genlib.misc import optree
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from migen.genlib import roundrobin
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from migen.bus.transactions import *
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from migen.sim.generic import Proxy
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@ -300,3 +301,83 @@ class Target(Module):
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else:
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s.wr(self.hub.call, 0)
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self._calling_tag = -1
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# Port sharing
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class SharedPort:
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def __init__(self, base_port):
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if not base_port.finalized:
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raise FinalizeError
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self.finalized = True
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nslots = len(base_port.slots)
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self.hub = base_port.hub
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self.base = base_port.base
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# 1 if that slot is assigned to us
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self.slots = [Signal() for i in range(nslots)]
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# request issuance
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self.adr = Signal(self.hub.aw)
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self.we = Signal()
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self.stb = Signal()
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if nslots > 1:
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self.tag_issue = Signal(max=nslots)
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self.ack = Signal()
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# request completion
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self.call = Signal()
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self.tag_call = Signal(self.hub.tagbits)
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self.dat_r = Signal(self.hub.dw)
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self.dat_w = Signal(self.hub.dw)
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self.dat_wm = Signal(self.hub.dw//8)
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def get_call_expression(self, slotn=0):
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if not self.finalized:
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raise FinalizeError
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return self.call \
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& (self.tag_call == (self.base + slotn))
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class PortSharer(Module):
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def __init__(self, base_port, nshares):
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self.shared_ports = [SharedPort(base_port) for i in range(nshares)]
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###
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# request issuance
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self.submodules.rr = roundrobin.RoundRobin(nshares, roundrobin.SP_CE)
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self.comb += [
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self.rr.request.eq(Cat(*[sp.stb for sp in self.shared_ports])),
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self.rr.ce.eq(base_port.ack)
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]
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self.comb += [
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base_port.adr.eq(Array(sp.adr for sp in self.shared_ports)[self.rr.grant]),
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base_port.we.eq(Array(sp.we for sp in self.shared_ports)[self.rr.grant]),
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base_port.stb.eq(Array(sp.stb for sp in self.shared_ports)[self.rr.grant]),
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]
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if hasattr(base_port, "tag_issue"):
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self.comb += [sp.tag_issue.eq(base_port.tag_issue) for sp in self.shared_ports]
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self.comb += [sp.ack.eq(base_port.ack & (self.rr.grant == n)) for n, sp in enumerate(self.shared_ports)]
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# request completion
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self.comb += [sp.call.eq(base_port.call & Array(sp.slots)[base_port.tag_call-base_port.base])
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for sp in self.shared_ports]
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self.comb += [sp.tag_call.eq(base_port.tag_call) for sp in self.shared_ports]
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self.comb += [sp.dat_r.eq(base_port.dat_r) for sp in self.shared_ports]
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self.comb += [
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base_port.dat_w.eq(optree("|", [sp.dat_w for sp in self.shared_ports])),
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base_port.dat_wm.eq(optree("|", [sp.dat_wm for sp in self.shared_ports])),
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]
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# request ownership tracking
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if hasattr(base_port, "tag_issue"):
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for sp in self.shared_ports:
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self.sync += If(sp.stb & sp.ack, Array(sp.slots)[sp.tag_issue].eq(1))
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for n, slot in enumerate(sp.slots):
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self.sync += If(base_port.call & (base_port.tag_call == (base_port.base + n)), slot.eq(0))
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else:
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for sp in self.shared_ports:
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self.sync += [
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If(sp.stb & sp.ack, sp.slots[0].eq(1)),
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If(base_port.call & (base_port.tag_call == base_port.base), sp.slots[0].eq(0))
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]
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