global: pep8 (E203)
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@ -58,11 +58,11 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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# init sequence
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# init sequence
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cmds = {
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cmds = {
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"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"PRECHARGE_ALL": "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"MODE_REGISTER": "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"AUTO_REFRESH" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
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"AUTO_REFRESH": "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
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"UNRESET" : "DFII_CONTROL_ODT|DFII_CONTROL_RESET_N",
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"UNRESET": "DFII_CONTROL_ODT|DFII_CONTROL_RESET_N",
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"CKE" : "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
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"CKE": "DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N"
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}
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}
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cl = sdram_phy_settings.cl
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cl = sdram_phy_settings.cl
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@ -147,11 +147,11 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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def format_mr0(cl, wr, dll_reset):
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def format_mr0(cl, wr, dll_reset):
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cl_to_mr0 = {
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cl_to_mr0 = {
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5 : 0b0010,
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5: 0b0010,
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6 : 0b0100,
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6: 0b0100,
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7 : 0b0110,
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7: 0b0110,
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8 : 0b1000,
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8: 0b1000,
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9 : 0b1010,
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9: 0b1010,
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10: 0b1100,
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10: 0b1100,
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11: 0b1110,
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11: 0b1110,
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12: 0b0001,
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12: 0b0001,
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@ -160,10 +160,10 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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}
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}
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wr_to_mr0 = {
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wr_to_mr0 = {
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16: 0b000,
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16: 0b000,
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5 : 0b001,
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5: 0b001,
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6 : 0b010,
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6: 0b010,
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7 : 0b011,
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7: 0b011,
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8 : 0b100,
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8: 0b100,
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10: 0b101,
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10: 0b101,
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12: 0b110,
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12: 0b110,
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14: 0b111
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14: 0b111
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