Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

generic_platform: do not create clock domains during Verilog conversion

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2013-03-18 18:44:58 +01:00
parent 4bf3190244
commit 797411c1a9
1 changed files with 2 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
mibuild/generic_platform.py
View file

@ -214,7 +214,8 @@ class GenericPlatform:
else:
frag = fragment
# generate Verilog
src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), return_ns=True, **kwargs)
src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(),
return_ns=True, create_clock_domains=False, **kwargs)
# resolve signal names in constraints
sc = self.constraint_manager.get_sig_constraints()
named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]