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create BaseSoC as a basic example design and build UDPSoC/EtherboneSoC on top of it

This commit is contained in:
Florent Kermarrec 2015-02-17 11:42:35 +01:00
parent eeaf03669a
commit 79a7f9ecb8
6 changed files with 282 additions and 324 deletions
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4
README
View File

@ -86,7 +86,7 @@ until new features are merged.
git clone https://github.com/enjoy-digital/liteeth
6. Build and load UDP loopback design (only for KC705 for now):
python3 make.py all (-s UDPSoCDevel to add LiteScopeLA)
python3 make.py -t udp all
7. Test design (only for KC705 for now):
try to ping 192.168.1.40
@ -95,7 +95,7 @@ until new features are merged.
run make test_udp
8. Build and load Etherbone design (only for KC705 for now):
python3 make.py -t Etherbone
python3 make.py -t etherbone all
9. Test design (only for KC705 for now):
try to ping 192.168.1.40

4
doc/source/docs/getting_started/downloads.rst
View File

@ -33,7 +33,7 @@ Download and install
- git clone https://github.com/enjoy-digital/liteeth
6. Build and load UDP loopback design (only for KC705 for now):
- python3 make.py all (-s UDPSoCDevel to add LiteScopeLA)
- python3 make.py -t udp all
7. Test design (only for KC705 for now):
- try to ping 192.168.1.40
@ -42,7 +42,7 @@ Download and install
- run make test_udp
8. Build and load Etherbone design (only for KC705 for now):
- python3 make.py -t Etherbone
- python3 make.py -t etherbone all
9. Test design (only for KC705 for now):
- try to ping 192.168.1.40

8
make.py
View File

@ -34,7 +34,7 @@ load-bitstream load bitstream into volatile storage.
all clean, build-csr-csv, build-bitstream, load-bitstream.
""")
parser.add_argument("-t", "--target", default="udp", help="Core type to build")
parser.add_argument("-t", "--target", default="base", help="Core type to build")
parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
parser.add_argument("-p", "--platform", default=None, help="platform to build for")
parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
@ -92,8 +92,14 @@ if __name__ == "__main__":
Ethernet core
====== Building options: ======
Platform: {}
Target: {}
Subtarget: {}
System Clk: {} MHz
===============================""".format(
platform_name,
args.target,
top_class.__name__,
soc.clk_freq/1000000
)
)

224
targets/base.py Normal file
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@ -0,0 +1,224 @@
import os
from migen.bank import csrgen
from migen.bus import wishbone, csr
from migen.bus import wishbone2csr
from migen.genlib.cdc import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.bank.description import *
from misoclib import identifier
from litescope.common import *
from litescope.bridge.uart2wb import LiteScopeUART2WB
from litescope.frontend.la import LiteScopeLA
from litescope.core.port import LiteScopeTerm
from liteeth.common import *
from liteeth.generic import *
from liteeth.phy.gmii import LiteEthPHYGMII
from liteeth.core import LiteEthUDPIPCore
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.reset = Signal()
clk200 = platform.request("clk200")
clk200_se = Signal()
self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
pll_locked = Signal()
pll_fb = Signal()
pll_sys = Signal()
self.specials += [
Instance("PLLE2_BASE",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
# VCO @ 1GHz
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 166MHz
p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
]
class GenSoC(Module):
csr_base = 0x00000000
csr_data_width = 32
csr_map = {
"bridge": 0,
"identifier": 1,
}
interrupt_map = {}
cpu_type = None
def __init__(self, platform, clk_freq):
self.clk_freq = clk_freq
# UART <--> Wishbone bridge
self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
# CSR bridge 0x00000000 (shadow @0x00000000)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
self._wb_masters = [self.bridge.wishbone]
self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
# CSR
self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
def add_wb_master(self, wbm):
if self.finalized:
raise FinalizeError
self._wb_masters.append(wbm)
def add_wb_slave(self, address_decoder, interface):
if self.finalized:
raise FinalizeError
self._wb_slaves.append((address_decoder, interface))
def add_cpu_memory_region(self, name, origin, length):
self.cpu_memory_regions.append((name, origin, length))
def add_cpu_csr_region(self, name, origin, busword, obj):
self.cpu_csr_regions.append((name, origin, busword, obj))
def do_finalize(self):
# Wishbone
self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
self._wb_slaves, register=True)
# CSR
self.submodules.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
data_width=self.csr_data_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
class BaseSoC(GenSoC, AutoCSR):
default_platform = "kc705"
csr_map = {
"phy": 11,
"core": 12
}
csr_map.update(GenSoC.csr_map)
def __init__(self, platform, clk_freq=166*1000000,
mac_address=0x10e2d5000000,
ip_address="192.168.1.40"):
GenSoC.__init__(self, platform, clk_freq)
self.submodules.crg = _CRG(platform)
# wishbone SRAM (to test Wishbone over UART and Etherbone)
self.submodules.sram = wishbone.SRAM(1024)
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
# ethernet PHY and UDP/IP stack
self.submodules.phy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)
class BaseSoCDevel(BaseSoC, AutoCSR):
csr_map = {
"la": 20
}
csr_map.update(BaseSoC.csr_map)
def __init__(self, platform):
BaseSoC.__init__(self, platform)
self.core_icmp_rx_fsm_state = Signal(4)
self.core_icmp_tx_fsm_state = Signal(4)
self.core_udp_rx_fsm_state = Signal(4)
self.core_udp_tx_fsm_state = Signal(4)
self.core_ip_rx_fsm_state = Signal(4)
self.core_ip_tx_fsm_state = Signal(4)
self.core_arp_rx_fsm_state = Signal(4)
self.core_arp_tx_fsm_state = Signal(4)
self.core_arp_table_fsm_state = Signal(4)
debug = (
# MAC interface
self.core.mac.core.sink.stb,
self.core.mac.core.sink.sop,
self.core.mac.core.sink.eop,
self.core.mac.core.sink.ack,
self.core.mac.core.sink.data,
self.core.mac.core.source.stb,
self.core.mac.core.source.sop,
self.core.mac.core.source.eop,
self.core.mac.core.source.ack,
self.core.mac.core.source.data,
# ICMP interface
self.core.icmp.echo.sink.stb,
self.core.icmp.echo.sink.sop,
self.core.icmp.echo.sink.eop,
self.core.icmp.echo.sink.ack,
self.core.icmp.echo.sink.data,
self.core.icmp.echo.source.stb,
self.core.icmp.echo.source.sop,
self.core.icmp.echo.source.eop,
self.core.icmp.echo.source.ack,
self.core.icmp.echo.source.data,
# IP interface
self.core.ip.crossbar.master.sink.stb,
self.core.ip.crossbar.master.sink.sop,
self.core.ip.crossbar.master.sink.eop,
self.core.ip.crossbar.master.sink.ack,
self.core.ip.crossbar.master.sink.data,
self.core.ip.crossbar.master.sink.ip_address,
self.core.ip.crossbar.master.sink.protocol,
# State machines
self.core_icmp_rx_fsm_state,
self.core_icmp_tx_fsm_state,
self.core_arp_rx_fsm_state,
self.core_arp_tx_fsm_state,
self.core_arp_table_fsm_state,
self.core_ip_rx_fsm_state,
self.core_ip_tx_fsm_state,
self.core_udp_rx_fsm_state,
self.core_udp_tx_fsm_state
)
self.submodules.la = LiteScopeLA(debug, 4096)
self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
def do_finalize(self):
BaseSoC.do_finalize(self)
self.comb += [
self.core_icmp_rx_fsm_state.eq(self.core.icmp.rx.fsm.state),
self.core_icmp_tx_fsm_state.eq(self.core.icmp.tx.fsm.state),
self.core_arp_rx_fsm_state.eq(self.core.arp.rx.fsm.state),
self.core_arp_tx_fsm_state.eq(self.core.arp.tx.fsm.state),
self.core_arp_table_fsm_state.eq(self.core.arp.table.fsm.state),
self.core_ip_rx_fsm_state.eq(self.core.ip.rx.fsm.state),
self.core_ip_tx_fsm_state.eq(self.core.ip.tx.fsm.state),
self.core_udp_rx_fsm_state.eq(self.core.udp.rx.fsm.state),
self.core_udp_tx_fsm_state.eq(self.core.udp.tx.fsm.state)
]
def do_exit(self, vns):
self.la.export(vns, "test/la.csv")
default_subtarget = BaseSoC

134
targets/etherbone.py
View File

@ -1,138 +1,23 @@
import os
from migen.bank import csrgen
from migen.bus import wishbone, csr
from migen.bus import wishbone2csr
from migen.genlib.cdc import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.bank.description import *
from misoclib import identifier
from litescope.common import *
from litescope.bridge.uart2wb import LiteScopeUART2WB
from litescope.frontend.la import LiteScopeLA
from litescope.core.port import LiteScopeTerm
from liteeth.common import *
from liteeth.generic import *
from liteeth.phy.gmii import LiteEthPHYGMII
from liteeth.core import LiteEthUDPIPCore
from targets.base import BaseSoC
from liteeth.core.etherbone import LiteEthEtherbone
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.reset = Signal()
clk200 = platform.request("clk200")
clk200_se = Signal()
self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
pll_locked = Signal()
pll_fb = Signal()
pll_sys = Signal()
self.specials += [
Instance("PLLE2_BASE",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
# VCO @ 1GHz
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 166MHz
p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
]
class GenSoC(Module):
csr_base = 0x00000000
csr_data_width = 32
csr_map = {
"bridge": 0,
"identifier": 1,
}
interrupt_map = {}
cpu_type = None
def __init__(self, platform, clk_freq):
self.clk_freq = clk_freq
# UART <--> Wishbone bridge
self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
# CSR bridge 0x00000000 (shadow @0x00000000)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
self._wb_masters = [self.bridge.wishbone]
self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
# CSR
self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
def add_wb_master(self, wbm):
if self.finalized:
raise FinalizeError
self._wb_masters.append(wbm)
def add_wb_slave(self, address_decoder, interface):
if self.finalized:
raise FinalizeError
self._wb_slaves.append((address_decoder, interface))
def add_cpu_memory_region(self, name, origin, length):
self.cpu_memory_regions.append((name, origin, length))
def add_cpu_csr_region(self, name, origin, busword, obj):
self.cpu_csr_regions.append((name, origin, busword, obj))
def do_finalize(self):
# Wishbone
self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
self._wb_slaves, register=True)
# CSR
self.submodules.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
data_width=self.csr_data_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
class EtherboneSoC(GenSoC, AutoCSR):
class EtherboneSoC(BaseSoC):
default_platform = "kc705"
csr_map = {
"phy": 11,
"core": 12
}
csr_map.update(GenSoC.csr_map)
def __init__(self, platform):
clk_freq = 166*1000000
GenSoC.__init__(self, platform, clk_freq)
self.submodules.crg = _CRG(platform)
# Ethernet PHY and UDP/IP
self.submodules.phy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.core = LiteEthUDPIPCore(self.phy, 0x10e2d5000000, convert_ip("192.168.1.40"), clk_freq)
# Etherbone
BaseSoC.__init__(self, platform,
mac_address=0x10e2d5000000,
ip_address="192.168.1.40")
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000)
self.add_wb_master(self.etherbone.master.bus)
self.submodules.sram = wishbone.SRAM(1024)
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
class EtherboneSoCDevel(EtherboneSoC, AutoCSR):
class EtherboneSoCDevel(EtherboneSoC):
csr_map = {
"la": 20
}
@ -177,13 +62,10 @@ class EtherboneSoCDevel(EtherboneSoC, AutoCSR):
self.etherbone.master.bus.bte,
self.etherbone.master.bus.err
)
self.submodules.la = LiteScopeLA(debug, 4096)
self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
def do_finalize(self):
EtherboneSoC.do_finalize(self)
def do_exit(self, vns):
self.la.export(vns, "test/la.csv")
default_subtarget = EtherboneSoC

232
targets/udp.py
View File

@ -1,223 +1,69 @@
import os
from migen.bank import csrgen
from migen.bus import wishbone, csr
from migen.bus import wishbone2csr
from migen.genlib.cdc import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from migen.bank.description import *
from misoclib import identifier
from litescope.common import *
from litescope.bridge.uart2wb import LiteScopeUART2WB
from litescope.frontend.la import LiteScopeLA
from litescope.core.port import LiteScopeTerm
from liteeth.common import *
from liteeth.generic import *
from liteeth.phy.gmii import LiteEthPHYGMII
from targets.base import BaseSoC
from liteeth.core import LiteEthUDPIPCore
class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.reset = Signal()
clk200 = platform.request("clk200")
clk200_se = Signal()
self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
pll_locked = Signal()
pll_fb = Signal()
pll_sys = Signal()
self.specials += [
Instance("PLLE2_BASE",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
# VCO @ 1GHz
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 166MHz
p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
]
class GenSoC(Module):
csr_base = 0x00000000
csr_data_width = 32
csr_map = {
"bridge": 0,
"identifier": 1,
}
interrupt_map = {}
cpu_type = None
def __init__(self, platform, clk_freq):
self.clk_freq = clk_freq
# UART <--> Wishbone bridge
self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
# CSR bridge 0x00000000 (shadow @0x00000000)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
self._wb_masters = [self.bridge.wishbone]
self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
# CSR
self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
def add_cpu_memory_region(self, name, origin, length):
self.cpu_memory_regions.append((name, origin, length))
def add_cpu_csr_region(self, name, origin, busword, obj):
self.cpu_csr_regions.append((name, origin, busword, obj))
def do_finalize(self):
# Wishbone
self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
self._wb_slaves, register=True)
# CSR
self.submodules.csrbankarray = csrgen.BankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
data_width=self.csr_data_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
class UDPSoC(GenSoC, AutoCSR):
class UDPSoC(BaseSoC):
default_platform = "kc705"
csr_map = {
"phy": 11,
"core": 12
}
csr_map.update(GenSoC.csr_map)
def __init__(self, platform):
clk_freq = 166*1000000
GenSoC.__init__(self, platform, clk_freq)
self.submodules.crg = _CRG(platform)
BaseSoC.__init__(self, platform,
mac_address=0x10e2d5000000,
ip_address="192.168.1.40")
# Ethernet PHY and UDP/IP
self.submodules.phy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.core = LiteEthUDPIPCore(self.phy, 0x10e2d5000000, convert_ip("192.168.1.40"), clk_freq)
# add udp loopback on port 6000 with dw=8
self.add_udp_loopback(6000, 8, 8192, "loopback_8")
# add udp loopback on port 8000 with dw=32
self.add_udp_loopback(8000, 32, 8192, "loopback_32")
# Create loopback on UDP port 6000 (dw=8)
loopback_port = self.core.udp.crossbar.get_port(6000, dw=8)
loopback_buffer = PacketBuffer(eth_udp_user_description(8), 8192, 8)
self.submodules += loopback_buffer
self.comb += Port.connect(loopback_port, loopback_buffer)
def add_udp_loopback(self, port, dw, depth, name=None):
port = self.core.udp.crossbar.get_port(port, dw)
buf = PacketBuffer(eth_udp_user_description(dw), depth//(dw//8), 8)
if name is None:
self.submodules += buf
else:
setattr(self.submodules, name, buf)
self.comb += Port.connect(port, buf)
# Create loopback on UDP port 8000 (dw=32)
loopback_port = self.core.udp.crossbar.get_port(8000, dw=32)
loopback_buffer = PacketBuffer(eth_udp_user_description(32), 2048, 8)
self.submodules += loopback_buffer
self.comb += Port.connect(loopback_port, loopback_buffer)
class UDPSoCDevel(UDPSoC, AutoCSR):
class UDPSoCDevel(UDPSoC):
csr_map = {
"la": 20
}
csr_map.update(UDPSoC.csr_map)
def __init__(self, platform):
UDPSoC.__init__(self, platform)
self.core_icmp_rx_fsm_state = Signal(4)
self.core_icmp_tx_fsm_state = Signal(4)
self.core_udp_rx_fsm_state = Signal(4)
self.core_udp_tx_fsm_state = Signal(4)
self.core_ip_rx_fsm_state = Signal(4)
self.core_ip_tx_fsm_state = Signal(4)
self.core_arp_rx_fsm_state = Signal(4)
self.core_arp_tx_fsm_state = Signal(4)
self.core_arp_table_fsm_state = Signal(4)
debug = (
self.core.mac.core.sink.stb,
self.core.mac.core.sink.sop,
self.core.mac.core.sink.eop,
self.core.mac.core.sink.ack,
self.core.mac.core.sink.data,
self.loopback_8.sink.stb,
self.loopback_8.sink.sop,
self.loopback_8.sink.eop,
self.loopback_8.sink.ack,
self.loopback_8.sink.data,
self.core.mac.core.source.stb,
self.core.mac.core.source.sop,
self.core.mac.core.source.eop,
self.core.mac.core.source.ack,
self.core.mac.core.source.data,
self.loopback_8.source.stb,
self.loopback_8.source.sop,
self.loopback_8.source.eop,
self.loopback_8.source.ack,
self.loopback_8.source.data,
self.core.icmp.echo.sink.stb,
self.core.icmp.echo.sink.sop,
self.core.icmp.echo.sink.eop,
self.core.icmp.echo.sink.ack,
self.core.icmp.echo.sink.data,
self.loopback_32.sink.stb,
self.loopback_32.sink.sop,
self.loopback_32.sink.eop,
self.loopback_32.sink.ack,
self.loopback_32.sink.data,
self.core.icmp.echo.source.stb,
self.core.icmp.echo.source.sop,
self.core.icmp.echo.source.eop,
self.core.icmp.echo.source.ack,
self.core.icmp.echo.source.data,
self.core.ip.crossbar.master.sink.stb,
self.core.ip.crossbar.master.sink.sop,
self.core.ip.crossbar.master.sink.eop,
self.core.ip.crossbar.master.sink.ack,
self.core.ip.crossbar.master.sink.data,
self.core.ip.crossbar.master.sink.ip_address,
self.core.ip.crossbar.master.sink.protocol,
self.phy.sink.stb,
self.phy.sink.sop,
self.phy.sink.eop,
self.phy.sink.ack,
self.phy.sink.data,
self.phy.source.stb,
self.phy.source.sop,
self.phy.source.eop,
self.phy.source.ack,
self.phy.source.data,
self.core_icmp_rx_fsm_state,
self.core_icmp_tx_fsm_state,
self.core_udp_rx_fsm_state,
self.core_udp_tx_fsm_state,
self.core_ip_rx_fsm_state,
self.core_ip_tx_fsm_state,
self.core_arp_rx_fsm_state,
self.core_arp_tx_fsm_state,
self.core_arp_table_fsm_state,
self.loopback_32.source.stb,
self.loopback_32.source.sop,
self.loopback_32.source.eop,
self.loopback_32.source.ack,
self.loopback_32.source.data
)
self.submodules.la = LiteScopeLA(debug, 4096)
self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
def do_finalize(self):
UDPSoC.do_finalize(self)
self.comb += [
self.core_icmp_rx_fsm_state.eq(self.core.icmp.rx.fsm.state),
self.core_icmp_tx_fsm_state.eq(self.core.icmp.tx.fsm.state),
self.core_udp_rx_fsm_state.eq(self.core.udp.rx.fsm.state),
self.core_udp_tx_fsm_state.eq(self.core.udp.tx.fsm.state),
self.core_ip_rx_fsm_state.eq(self.core.ip.rx.fsm.state),
self.core_ip_tx_fsm_state.eq(self.core.ip.tx.fsm.state),
self.core_arp_rx_fsm_state.eq(self.core.arp.rx.fsm.state),
self.core_arp_tx_fsm_state.eq(self.core.arp.tx.fsm.state),
self.core_arp_table_fsm_state.eq(self.core.arp.table.fsm.state)
]
def do_exit(self, vns):
self.la.export(vns, "test/la.csv")