interconnect/axi/AXIBurst2Beat: Fix BURST_WRAP case.
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@ -317,7 +317,7 @@ class AXIBurst2Beat(Module):
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beat_count = Signal(8)
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beat_size = Signal(8 + 4)
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beat_offset = Signal(8 + 4)
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beat_offset = Signal((8 + 4, True))
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beat_wrap = Signal(8 + 4)
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# Compute parameters
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@ -352,8 +352,8 @@ class AXIBurst2Beat(Module):
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)
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),
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If((ax_burst.burst == BURST_WRAP) & (BURST_WRAP in capabilities),
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If(beat_offset == beat_wrap,
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beat_offset.eq(0)
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If((ax_beat.addr & beat_wrap) == beat_wrap,
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beat_offset.eq(beat_offset - beat_wrap)
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)
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)
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)
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@ -23,13 +23,20 @@ class Burst:
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def to_beats(self):
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r = []
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for i in range(self.len + 1):
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burst_length = self.len + 1
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burst_size = 2**self.size
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for i in range(burst_length):
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if self.type == BURST_INCR:
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offset = i*2**(self.size)
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r += [Beat(self.addr + offset)]
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elif self.type == BURST_WRAP:
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offset = (i*2**(self.size))%((2**self.size)*(self.len + 1))
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r += [Beat(self.addr + offset)]
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assert burst_length in [2, 4, 8, 16]
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assert (self.addr % burst_size) == 0
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burst_base = self.addr - self.addr % (burst_length * burst_size)
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burst_offset = self.addr % (burst_length * burst_size)
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burst_addr = burst_base + (burst_offset + i*burst_size) % (burst_length * burst_size)
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#print("0x{:08x}".format(burst_addr))
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r += [Beat(burst_addr)]
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else:
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r += [Beat(self.addr)]
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return r
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@ -86,6 +93,7 @@ class TestAXI(unittest.TestCase):
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yield ax.ready.eq(0)
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yield
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ax_addr = (yield ax.addr)
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#print("0x{:08x}".format(ax_addr))
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if ax_addr != beat.addr:
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self.errors += 1
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yield
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@ -102,6 +110,7 @@ class TestAXI(unittest.TestCase):
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bursts.append(Burst(prng.randrange(2**32), BURST_FIXED, prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(prng.randrange(2**32), BURST_INCR, prng.randrange(255), log2_int(32//8)))
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bursts.append(Burst(4, BURST_WRAP, 4-1, log2_int(2)))
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bursts.append(Burst(0x80000160, BURST_WRAP, 0x3, 0b100))
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# generate expected dut output (beats for reference)
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beats = []
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