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interconnect/axi/AXIBurst2Beat: Fix BURST_WRAP case.

This commit is contained in:
Florent Kermarrec 2021-08-06 16:41:28 +02:00
parent ce5864983d
commit 79ac09316a
2 changed files with 15 additions and 6 deletions
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6
litex/soc/interconnect/axi.py
View File

@ -317,7 +317,7 @@ class AXIBurst2Beat(Module):
beat_count = Signal(8) beat_count = Signal(8)
beat_size = Signal(8 + 4) beat_size = Signal(8 + 4)
beat_offset = Signal(8 + 4) beat_offset = Signal((8 + 4, True))
beat_wrap = Signal(8 + 4) beat_wrap = Signal(8 + 4)
# Compute parameters # Compute parameters
@ -352,8 +352,8 @@ class AXIBurst2Beat(Module):
) )
), ),
If((ax_burst.burst == BURST_WRAP) & (BURST_WRAP in capabilities), If((ax_burst.burst == BURST_WRAP) & (BURST_WRAP in capabilities),
If(beat_offset == beat_wrap, If((ax_beat.addr & beat_wrap) == beat_wrap,
beat_offset.eq(0) beat_offset.eq(beat_offset - beat_wrap)
) )
) )
) )

15
test/test_axi.py
View File

@ -23,13 +23,20 @@ class Burst:
def to_beats(self): def to_beats(self):
r = [] r = []
for i in range(self.len + 1): burst_length = self.len + 1
burst_size = 2**self.size
for i in range(burst_length):
if self.type == BURST_INCR: if self.type == BURST_INCR:
offset = i*2**(self.size) offset = i*2**(self.size)
r += [Beat(self.addr + offset)] r += [Beat(self.addr + offset)]
elif self.type == BURST_WRAP: elif self.type == BURST_WRAP:
offset = (i*2**(self.size))%((2**self.size)*(self.len + 1)) assert burst_length in [2, 4, 8, 16]
r += [Beat(self.addr + offset)] assert (self.addr % burst_size) == 0
burst_base = self.addr - self.addr % (burst_length * burst_size)
burst_offset = self.addr % (burst_length * burst_size)
burst_addr = burst_base + (burst_offset + i*burst_size) % (burst_length * burst_size)
#print("0x{:08x}".format(burst_addr))
r += [Beat(burst_addr)]
else: else:
r += [Beat(self.addr)] r += [Beat(self.addr)]
return r return r
@ -86,6 +93,7 @@ class TestAXI(unittest.TestCase):
yield ax.ready.eq(0) yield ax.ready.eq(0)
yield yield
ax_addr = (yield ax.addr) ax_addr = (yield ax.addr)
#print("0x{:08x}".format(ax_addr))
if ax_addr != beat.addr: if ax_addr != beat.addr:
self.errors += 1 self.errors += 1
yield yield
@ -102,6 +110,7 @@ class TestAXI(unittest.TestCase):
bursts.append(Burst(prng.randrange(2**32), BURST_FIXED, prng.randrange(255), log2_int(32//8))) bursts.append(Burst(prng.randrange(2**32), BURST_FIXED, prng.randrange(255), log2_int(32//8)))
bursts.append(Burst(prng.randrange(2**32), BURST_INCR, prng.randrange(255), log2_int(32//8))) bursts.append(Burst(prng.randrange(2**32), BURST_INCR, prng.randrange(255), log2_int(32//8)))
bursts.append(Burst(4, BURST_WRAP, 4-1, log2_int(2))) bursts.append(Burst(4, BURST_WRAP, 4-1, log2_int(2)))
bursts.append(Burst(0x80000160, BURST_WRAP, 0x3, 0b100))
# generate expected dut output (beats for reference) # generate expected dut output (beats for reference)
beats = [] beats = []