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Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.

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Sebastien Bourdeauducq 2012-11-28 22:49:22 +01:00
parent 0620e75cb8
commit 79e5f24a65
1 changed files with 2 additions and 1 deletions
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3
milkymist/asmicon/multiplexer.py
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@ -251,9 +251,10 @@ class Multiplexer:
) )
fsm.act(fsm.REFRESH, fsm.act(fsm.REFRESH,
steerer.sel[0].eq(STEER_REFRESH), steerer.sel[0].eq(STEER_REFRESH),
self.refresher.ack.eq(1),
If(~self.refresher.req, fsm.next_state(fsm.READ)) If(~self.refresher.req, fsm.next_state(fsm.READ))
) )
# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
comb.append(self.refresher.ack.eq(fsm._state == fsm.REFRESH))
return Fragment(comb, sync) + \ return Fragment(comb, sync) + \
choose_cmd.get_fragment() + \ choose_cmd.get_fragment() + \