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bus/csr/SRAM: support init

This commit is contained in:
Sebastien Bourdeauducq 2013-05-19 20:53:37 +02:00
parent 27accd72b5
commit 7ada0159fd
1 changed files with 2 additions and 2 deletions
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4
migen/bus/csr.py
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@ -55,11 +55,11 @@ def _compute_page_bits(nwords):
return 0
class SRAM(Module):
def __init__(self, mem_or_size, address, read_only=None, bus=None):
def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None):
if isinstance(mem_or_size, Memory):
mem = mem_or_size
else:
mem = Memory(data_width, mem_or_size//(data_width//8))
mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
if mem.width > data_width:
csrw_per_memw = (mem.width + data_width - 1)//data_width
word_bits = bits_for(csrw_per_memw-1)