build/xilinx/vivado: synth_mode -> self._synth_mode.
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@ -357,7 +357,7 @@ class XilinxVivadoToolchain(GenericToolchain):
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return script_file
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def run_script(self, script):
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if synth_mode == "yosys":
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if self._synth_mode == "yosys":
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common._run_yosys(self.platform.device, self.platform.sources,
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self.platform.verilog_include_paths, self._build_name)
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if sys.platform in ["win32", "cygwin"]:
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