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Merge pull request #57 from rohitk-singh/master 

WIP - BIOS: Flashboot without main ram
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enjoy-digital 2018-02-10 21:37:38 +01:00 committed by GitHub
parent c14502807e 75e7f9505a
commit 7b5bd4041a
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 16 additions and 2 deletions
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18
litex/soc/software/bios/boot.c
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@ -290,6 +290,17 @@ void netboot(void)
#endif #endif
#ifdef FLASH_BOOT_ADDRESS #ifdef FLASH_BOOT_ADDRESS
/* On systems with exernal SDRAM we copy out of the SPI flash into the SDRAM
before running, as it is faster. If we have no SDRAM then we have to
execute directly out of the SPI flash. */
#ifdef MAIN_RAM_BASE
#define FIRMWARE_BASE_ADDRESS MAIN_RAM_BASE
#else
/* Firmware code starts after (a) length and (b) CRC -- both unsigned ints */
#define FIRMWARE_BASE_ADDRESS (FLASH_BOOT_ADDRESS + 2 * sizeof(unsigned int))
#endif
void flashboot(void) void flashboot(void)
{ {
unsigned int *flashbase; unsigned int *flashbase;
@ -306,14 +317,17 @@ void flashboot(void)
return; return;
} }
#ifdef MAIN_RAM_BASE
printf("Loading %d bytes from flash...\n", length); printf("Loading %d bytes from flash...\n", length);
memcpy((void *)MAIN_RAM_BASE, flashbase, length); memcpy((void *)MAIN_RAM_BASE, flashbase, length);
got_crc = crc32((unsigned char *)MAIN_RAM_BASE, length); #endif
got_crc = crc32((unsigned char *)FIRMWARE_BASE_ADDRESS, length);
if(crc != got_crc) { if(crc != got_crc) {
printf("CRC failed (expected %08x, got %08x)\n", crc, got_crc); printf("CRC failed (expected %08x, got %08x)\n", crc, got_crc);
return; return;
} }
boot(0, 0, 0, MAIN_RAM_BASE); boot(0, 0, 0, FIRMWARE_BASE_ADDRESS);
} }
#endif #endif