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sim: support clock domains without sync

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This commit is contained in:
Sebastien Bourdeauducq 2015-09-12 15:12:57 +08:00
parent fd986210f8
commit 7bd72a16df
1 changed files with 21 additions and 20 deletions
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3
migen/sim.py
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@ -148,7 +148,6 @@ class Simulator:
modified = self.evaluator.commit() modified = self.evaluator.commit()
def _process_generators(self, cd): def _process_generators(self, cd):
if cd in self.generators:
exhausted = [] exhausted = []
for generator in self.generators[cd]: for generator in self.generators[cd]:
reply = None reply = None
@ -178,7 +177,9 @@ class Simulator:
while True: while True:
cds = self.time.tick() cds = self.time.tick()
for cd in cds: for cd in cds:
if cd in self.fragment.sync:
self.evaluator.execute(self.fragment.sync[cd]) self.evaluator.execute(self.fragment.sync[cd])
if cd in self.generators:
self._process_generators(cd) self._process_generators(cd)
self._comb_propagate(self.evaluator.commit()) self._comb_propagate(self.evaluator.commit())